📄 mlt.twr
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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
D:/Xilinx/bin/nt/trce.exe -ise e:\temp\spartan2\veriloge\basic\mlt\mlt.ise
-intstyle ise -e 3 -l 3 -s 6 -xml mlt mlt.ncd -o mlt.twr mlt.pcf
Design file: mlt.ncd
Physical constraint file: mlt.pcf
Device,speed: xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
a<0> |c<1> | 12.287|
a<0> |c<2> | 12.095|
a<0> |c<3> | 11.619|
a<0> |c<4> | 12.350|
a<0> |c<5> | 12.127|
a<0> |c<6> | 11.928|
a<0> |c<7> | 11.990|
a<1> |c<1> | 12.233|
a<1> |c<2> | 12.036|
a<1> |c<3> | 11.565|
a<1> |c<4> | 12.296|
a<1> |c<5> | 12.073|
a<1> |c<6> | 11.736|
a<1> |c<7> | 11.841|
b<0> |c<1> | 12.480|
b<0> |c<2> | 12.288|
b<0> |c<3> | 11.812|
b<0> |c<4> | 12.543|
b<0> |c<5> | 12.320|
b<0> |c<6> | 12.121|
b<0> |c<7> | 12.183|
b<1> |c<1> | 12.073|
b<1> |c<2> | 11.973|
b<1> |c<3> | 11.341|
b<1> |c<4> | 12.072|
b<1> |c<5> | 11.849|
b<1> |c<6> | 11.759|
b<1> |c<7> | 11.864|
---------------+---------------+---------+
Analysis completed Fri Feb 24 15:29:26 2006
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Peak Memory Usage: 62 MB
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