📄 bcd.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: bcd Date: 2-21-2006, 2:29PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
30 /144 ( 21%) 103 /720 ( 14%) 82 /432 ( 19%) 22 /144 ( 15%) 15 /117 ( 13%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 6/18 22/54 21/90 0/15
FB2 0/18 0/54 0/90 0/15
FB3 0/18 0/54 0/90 0/15
FB4 3/18 28/54 11/90 3/15
FB5 0/18 0/54 0/90 0/14
FB6 18/18* 22/54 63/90 6/13
FB7 0/18 0/54 0/90 0/15
FB8 3/18 10/54 8/90 1/15
----- ----- ----- -----
30/144 82/432 103/720 10/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 6 6 | I/O : 16 109
Output : 10 10 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 16 16
** Power Data **
There are 30 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 10 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
c<1> 5 6 FB4_1 118 I/O O STD FAST
en<1> 3 23 FB4_9 131 I/O O STD FAST RESET
en<0> 3 23 FB4_11 132 I/O O STD FAST RESET
c<7> 6 6 FB6_2 106 I/O O STD FAST
c<5> 2 6 FB6_4 111 I/O O STD FAST
c<4> 7 6 FB6_8 113 I/O O STD FAST
c<2> 7 6 FB6_9 116 I/O O STD FAST
c<3> 5 6 FB6_10 115 I/O O STD FAST
c<0> 0 0 FB6_11 119 I/O O STD FAST
c<6> 3 6 FB8_16 107 I/O O STD FAST
** 20 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
cnt<19> 3 22 FB1_13 STD RESET
cnt<16> 3 19 FB1_14 STD RESET
cnt<15> 3 18 FB1_15 STD RESET
cnt<14> 3 17 FB1_16 STD RESET
cnt<18> 4 22 FB1_17 STD RESET
cnt<17> 5 22 FB1_18 STD RESET
cnt<9> 3 12 FB6_1 STD RESET
cnt<8> 3 11 FB6_3 STD RESET
cnt<7> 3 10 FB6_5 STD RESET
cnt<6> 3 9 FB6_6 STD RESET
cnt<5> 3 8 FB6_7 STD RESET
cnt<4> 3 7 FB6_12 STD RESET
cnt<3> 3 6 FB6_13 STD RESET
cnt<2> 3 5 FB6_14 STD RESET
cnt<13> 3 16 FB6_15 STD RESET
cnt<12> 3 15 FB6_16 STD RESET
cnt<11> 3 14 FB6_17 STD RESET
cnt<10> 3 13 FB6_18 STD RESET
cnt<0> 2 3 FB8_17 STD RESET
cnt<1> 3 4 FB8_18 STD RESET
** 6 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
a<3> FB2_17 15 I/O I
clk FB4_5 128 I/O I
a<1> FB5_7 66 I/O I
a<2> FB5_14 61 I/O I
a<0> FB5_17 69 I/O I
rst FB7_2 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 22/32
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 23 I/O
(unused) 0 0 0 5 FB1_2 16 I/O
(unused) 0 0 0 5 FB1_3 17 I/O
(unused) 0 0 0 5 FB1_4 25 I/O
(unused) 0 0 0 5 FB1_5 19 I/O
(unused) 0 0 0 5 FB1_6 20 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 21 I/O
(unused) 0 0 0 5 FB1_9 22 I/O
(unused) 0 0 0 5 FB1_10 31 I/O
(unused) 0 0 0 5 FB1_11 24 I/O
(unused) 0 0 0 5 FB1_12 26 I/O
cnt<19> 3 0 0 2 FB1_13 (b) (b)
cnt<16> 3 0 0 2 FB1_14 27 I/O (b)
cnt<15> 3 0 0 2 FB1_15 28 I/O (b)
cnt<14> 3 0 0 2 FB1_16 35 I/O (b)
cnt<18> 4 0 0 1 FB1_17 30 GCK/I/O (b)
cnt<17> 5 0 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 9: cnt<16> 16: cnt<4>
2: cnt<0> 10: cnt<17> 17: cnt<5>
3: cnt<10> 11: cnt<18> 18: cnt<6>
4: cnt<11> 12: cnt<19> 19: cnt<7>
5: cnt<12> 13: cnt<1> 20: cnt<8>
6: cnt<13> 14: cnt<2> 21: cnt<9>
7: cnt<14> 15: cnt<3> 22: rst
8: cnt<15>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
cnt<19> XXXXXXXXXXXXXXXXXXXXXX.................. 22
cnt<16> XXXXXXXXX...XXXXXXXXXX.................. 19
cnt<15> XXXXXXXX....XXXXXXXXXX.................. 18
cnt<14> XXXXXXX.....XXXXXXXXXX.................. 17
cnt<18> XXXXXXXXXXXXXXXXXXXXXX.................. 22
cnt<17> XXXXXXXXXXXXXXXXXXXXXX.................. 22
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 142 I/O
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 0 5 FB2_5 2 GTS/I/O
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 0 5 FB2_11 9 I/O
(unused) 0 0 0 5 FB2_12 10 I/O
(unused) 0 0 0 5 FB2_13 12 I/O
(unused) 0 0 0 5 FB2_14 11 I/O
(unused) 0 0 0 5 FB2_15 13 I/O
(unused) 0 0 0 5 FB2_16 14 I/O
(unused) 0 0 0 5 FB2_17 15 I/O I
(unused) 0 0 0 5 FB2_18 (b)
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 39 I/O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
(unused) 0 0 0 5 FB3_3 41 I/O
(unused) 0 0 0 5 FB3_4 44 I/O
(unused) 0 0 0 5 FB3_5 33 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 46 I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
(unused) 0 0 0 5 FB3_9 40 I/O
(unused) 0 0 0 5 FB3_10 48 I/O
(unused) 0 0 0 5 FB3_11 43 I/O
(unused) 0 0 0 5 FB3_12 45 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 49 I/O
(unused) 0 0 0 5 FB3_15 50 I/O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 51 I/O
(unused) 0 0 0 5 FB3_18 (b)
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 28/26
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
c<1> 5 0 0 0 FB4_1 118 I/O O
(unused) 0 0 0 5 FB4_2 126 I/O
(unused) 0 0 0 5 FB4_3 133 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 128 I/O I
(unused) 0 0 0 5 FB4_6 129 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 130 I/O
en<1> 3 0 0 2 FB4_9 131 I/O O
(unused) 0 0 0 5 FB4_10 135 I/O
en<0> 3 0 0 2 FB4_11 132 I/O O
(unused) 0 0 0 5 FB4_12 134 I/O
(unused) 0 0 0 5 FB4_13 137 I/O
(unused) 0 0 0 5 FB4_14 136 I/O
(unused) 0 0 0 5 FB4_15 138 I/O
(unused) 0 0 0 5 FB4_16 139 I/O
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