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📄 bcd.twr

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 TWR
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--------------------------------------------------------------------------------
Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise e:\temp\spartan2\veriloge\basic\bcd\bcd.ise
-intstyle ise -e 3 -l 3 -s 6 -xml bcd bcd.ncd -o bcd.twr bcd.pcf


Design file:              bcd.ncd
Physical constraint file: bcd.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
rst         |    3.501(R)|   -0.417(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
c<1>        |   13.169(R)|clk_BUFGP         |   0.000|
c<2>        |   12.828(R)|clk_BUFGP         |   0.000|
c<3>        |   13.294(R)|clk_BUFGP         |   0.000|
c<4>        |   13.510(R)|clk_BUFGP         |   0.000|
c<5>        |   13.654(R)|clk_BUFGP         |   0.000|
c<6>        |   12.936(R)|clk_BUFGP         |   0.000|
c<7>        |   13.040(R)|clk_BUFGP         |   0.000|
en<0>       |    9.112(R)|clk_BUFGP         |   0.000|
en<1>       |    9.081(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    8.490|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
a<0>           |c<1>           |   11.669|
a<0>           |c<2>           |   11.374|
a<0>           |c<3>           |   11.875|
a<0>           |c<4>           |   11.532|
a<0>           |c<5>           |   12.107|
a<0>           |c<6>           |   11.569|
a<0>           |c<7>           |   11.397|
a<1>           |c<1>           |   12.545|
a<1>           |c<2>           |   12.250|
a<1>           |c<3>           |   12.751|
a<1>           |c<4>           |   12.408|
a<1>           |c<5>           |   12.983|
a<1>           |c<6>           |   12.445|
a<1>           |c<7>           |   12.273|
a<2>           |c<1>           |   12.604|
a<2>           |c<2>           |   12.263|
a<2>           |c<3>           |   12.724|
a<2>           |c<4>           |   12.945|
a<2>           |c<5>           |   13.089|
a<2>           |c<6>           |   12.408|
a<2>           |c<7>           |   12.401|
a<3>           |c<1>           |   10.838|
a<3>           |c<2>           |   10.543|
a<3>           |c<3>           |   11.044|
a<3>           |c<4>           |   11.072|
a<3>           |c<5>           |   11.276|
a<3>           |c<6>           |   10.738|
a<3>           |c<7>           |   10.566|
---------------+---------------+---------+

Analysis completed Tue Mar 14 15:44:14 2006
--------------------------------------------------------------------------------



Peak Memory Usage: 62 MB

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