bcd.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: bcd.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "bcd.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "bcd"
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : bcd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : bcd.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "bcd.v"
Module <bcd> compiled
No errors in compilation
Analysis of file <"bcd.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <bcd>.
WARNING:Xst:905 - "bcd.v" line 40: The signals <code_data> are missing in the sensitivity list of always block.
Module <bcd> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <bcd>.
    Related source file is "bcd.v".
    Found 16x8-bit ROM for signal <c>.
    Found 2-bit register for signal <en>.
    Found 4-bit 4-to-1 multiplexer for signal <c_tmp>.
    Found 20-bit up counter for signal <cnt>.
    Found 4-bit 8-to-1 multiplexer for signal <code_data<4:1>>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred   8 Multiplexer(s).
Unit <bcd> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Counters                         : 1
 20-bit up counter                 : 1
# Registers                        : 1
 2-bit register                    : 1
# Multiplexers                     : 5
 1-bit 8-to-1 multiplexer          : 4
 4-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <bcd> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block bcd, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : bcd.ngr
Top Level Output File Name         : bcd
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 16

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 3
#      1-bit register              : 2
#      20-bit register             : 1
# Multiplexers                     : 5
#      1-bit 8-to-1 multiplexer    : 4
#      4-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 1
#      20-bit adder                : 1

Cell Usage :
# BELS                             : 88
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 19
#      LUT2                        : 2
#      LUT2_L                      : 1
#      LUT3                        : 3
#      LUT3_D                      : 1
#      LUT4                        : 17
#      LUT4_D                      : 1
#      MUXCY                       : 19
#      VCC                         : 1
#      XORCY                       : 19
# FlipFlops/Latches                : 22
#      FDR                         : 20
#      FDRE                        : 1
#      FDSE                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 15
#      IBUF                        : 5
#      OBUF                        : 10
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      28  out of    768     3%  
 Number of Slice Flip Flops:            22  out of   1536     1%  
 Number of 4 input LUTs:                44  out of   1536     2%  
 Number of bonded IOBs:                 16  out of     96    16%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 22    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.893ns (Maximum Frequency: 112.448MHz)
   Minimum input arrival time before clock: 5.371ns
   Maximum output required time after clock: 12.890ns
   Maximum combinational path delay: 12.356ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 8.893ns (frequency: 112.448MHz)
  Total number of paths / destination ports: 652 / 44
-------------------------------------------------------------------------
Delay:               8.893ns (Levels of Logic = 3)
  Source:            cnt_8 (FF)
  Destination:       cnt_18 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_8 to cnt_18
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  cnt_8 (cnt_8)
     LUT4:I0->O            2   0.549   1.206  _n000134 (CHOICE72)
     LUT3_D:I0->O          1   0.549   1.035  _n00001_SW0 (N49)
     LUT4:I3->O           10   0.549   1.980  _n00001_1 (_n00001)
     FDR:R                     0.734          cnt_18
    ----------------------------------------
    Total                      8.893ns (3.466ns logic, 5.427ns route)
                                       (39.0% logic, 61.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 22 / 22
-------------------------------------------------------------------------
Offset:              5.371ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       cnt_18 (FF)
  Destination Clock: clk rising

  Data Path: rst to cnt_18
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.776   1.332  rst_IBUF (rst_IBUF)
     LUT4:I0->O           10   0.549   1.980  _n00001 (_n0000)
     FDR:R                     0.734          cnt_0
    ----------------------------------------
    Total                      5.371ns (2.059ns logic, 3.312ns route)
                                       (38.3% logic, 61.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 58 / 9
-------------------------------------------------------------------------
Offset:              12.890ns (Levels of Logic = 4)
  Source:            en_1 (FF)
  Destination:       c<7> (PAD)
  Source Clock:      clk rising

  Data Path: en_1 to c<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             6   1.085   1.665  en_1 (en_1)
     LUT2:I0->O            1   0.549   1.035  c_tmp<1>1 (N11)
     LUT4:I2->O            7   0.549   1.755  c_tmp<1>2 (c_tmp<1>)
     LUT4:I1->O            1   0.549   1.035  Mrom_c_inst_lut4_71 (c_7_OBUF)
     OBUF:I->O                 4.668          c_7_OBUF (c<7>)
    ----------------------------------------
    Total                     12.890ns (7.400ns logic, 5.490ns route)
                                       (57.4% logic, 42.6% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 91 / 7
-------------------------------------------------------------------------
Delay:               12.356ns (Levels of Logic = 5)
  Source:            a<1> (PAD)
  Destination:       c<7> (PAD)

  Data Path: a<1> to c<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.776   1.440  a_1_IBUF (a_1_IBUF)
     LUT3:I0->O            1   0.549   1.035  c_tmp<0>1_SW0 (N45)
     LUT4:I2->O            7   0.549   1.755  c_tmp<0>1 (c_tmp<0>)
     LUT4:I0->O            1   0.549   1.035  Mrom_c_inst_lut4_71 (c_7_OBUF)
     OBUF:I->O                 4.668          c_7_OBUF (c<7>)
    ----------------------------------------
    Total                     12.356ns (7.091ns logic, 5.265ns route)
                                       (57.4% logic, 42.6% route)

=========================================================================
CPU : 4.88 / 5.30 s | Elapsed : 5.00 / 5.00 s
 
--> 

Total memory usage is 74148 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)