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📄 sub.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
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	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & !b<1> & !a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
;Imported pterms FB5_17
	# a<0> & b<0> & a<1> & b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 5 | 0 | EXP24_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 5 | 1
INPUTS | 8 | a<0>  | b<0>  | c<3>  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | c<4>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | a<2>  | b<2>
INPUTMC | 4 | 5 | 9 | 5 | 15 | 5 | 7 | 3 | 17
INPUTP | 4 | 77 | 66 | 72 | 63
EXPORTS | 1 | 5 | 1
EQ | 11 | 
       EXP24_.EXP  =  a<0> & !b<0> & !c<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# c<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<2> & b<2> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & !b<2> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 5 | 2 | EXP25_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 5 | 1
INPUTS | 9 | a<2>  | b<2>  | c<4>  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | a<0>  | b<0>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | _10_.EXP
INPUTMC | 5 | 5 | 7 | 5 | 15 | 3 | 17 | 4 | 16 | 5 | 3
INPUTP | 4 | 72 | 63 | 77 | 66
EXPORTS | 1 | 5 | 1
IMPORTS | 1 | 5 | 3
EQ | 29 | 
       EXP25_.EXP  =  a<2> & !b<2> & c<4> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<2> & b<2> & c<4> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_4
	# !a<0> & b<0> & !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<2> & !b<2> & !c<3> & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & b<2> & !c<3> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 6 | 13 | EXP26_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 6 | 14
INPUTS | 9 | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | a<0>  | a<1>  | b<1>  | c<3>  | b<0>  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
INPUTMC | 3 | 3 | 17 | 5 | 9 | 5 | 17
INPUTP | 6 | 72 | 63 | 77 | 74 | 64 | 66
EXPORTS | 1 | 6 | 14
EQ | 7 | 
       EXP26_.EXP  =  !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & a<1> & !b<1> & c<3>
	# !a<0> & b<0> & !a<1> & b<1>
	# !a<1> & b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 6 | 14 | EXP27_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 6 | 15
INPUTS | 10 | a<1>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | b<1>  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | a<2>  | a<0>  | b<0>  | c<3>  | EXP26_.EXP
INPUTMC | 4 | 3 | 17 | 5 | 17 | 5 | 9 | 6 | 13
INPUTP | 6 | 74 | 63 | 64 | 72 | 77 | 66
EXPORTS | 1 | 6 | 15
IMPORTS | 1 | 6 | 13
EQ | 18 | 
       EXP27_.EXP  =  a<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & !a<2> & b<2> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<0> & b<0> & a<1> & !b<1> & !c<3>
;Imported pterms FB7_14
	# !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & a<1> & !b<1> & c<3>
	# !a<0> & b<0> & !a<1> & b<1>
	# !a<1> & b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 6 | 16 | EXP28_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 6 | 15
INPUTS | 8 | a<1>  | b<1>  | c<3>  | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | EXP29_.EXP
INPUTMC | 4 | 5 | 9 | 3 | 17 | 5 | 17 | 6 | 17
INPUTP | 4 | 74 | 64 | 72 | 63
EXPORTS | 1 | 6 | 15
IMPORTS | 1 | 6 | 17
EQ | 18 | 
       EXP28_.EXP  =  !a<1> & b<1> & c<3>
	# a<2> & b<2> & c<3>
	# a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<2> & !b<2> & c<3>
	# !a<1> & !b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB7_18
	# !b<0> & a<1> & !b<1> & c<3>
	# a<0> & !b<0> & a<1> & b<1> & !c<3>
	# a<0> & !b<0> & !a<1> & !b<1> & !c<3>
	# !a<1> & b<1> & a<2> & !b<2> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & b<1> & !a<2> & b<2> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 6 | 17 | EXP29_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 6 | 16
INPUTS | 9 | b<0>  | a<1>  | b<1>  | c<3>  | a<0>  | a<2>  | b<2>  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
INPUTMC | 3 | 5 | 9 | 5 | 17 | 3 | 17
INPUTP | 6 | 66 | 74 | 64 | 77 | 72 | 63
EXPORTS | 1 | 6 | 16
EQ | 9 | 
       EXP29_.EXP  =  !b<0> & a<1> & !b<1> & c<3>
	# a<0> & !b<0> & a<1> & b<1> & !c<3>
	# a<0> & !b<0> & !a<1> & !b<1> & !c<3>
	# !a<1> & b<1> & a<2> & !b<2> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & b<1> & !a<2> & b<2> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 7 | 13 | EXP30_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 7 | 14
INPUTS | 8 | a<0>  | b<0>  | a<1>  | b<1>  | c<3>  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
INPUTMC | 4 | 5 | 9 | 5 | 17 | 3 | 17 | 5 | 14
INPUTP | 4 | 77 | 66 | 74 | 64
EXPORTS | 1 | 7 | 14
EQ | 12 | 
       EXP30_.EXP  =  !a<0> & b<0> & a<1> & b<1> & !c<3> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 7 | 14 | EXP31_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 7 | 15
INPUTS | 9 | a<0>  | a<1>  | b<1>  | c<3>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | b<0>  | EXP30_.EXP
INPUTMC | 5 | 5 | 9 | 5 | 14 | 5 | 17 | 3 | 17 | 7 | 13
INPUTP | 4 | 77 | 74 | 64 | 66
EXPORTS | 1 | 7 | 15
IMPORTS | 1 | 7 | 13
EQ | 25 | 
       EXP31_.EXP  =  a<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# a<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & !b<1> & c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !b<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !b<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_14
	# !a<0> & b<0> & a<1> & b<1> & !c<3> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 7 | 16 | EXP32_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 7 | 15
INPUTS | 9 | a<0>  | b<0>  | a<1>  | b<1>  | c<3>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | EXP33_.EXP
INPUTMC | 5 | 5 | 9 | 5 | 14 | 3 | 17 | 5 | 17 | 7 | 17
INPUTP | 4 | 77 | 66 | 74 | 64
EXPORTS | 1 | 7 | 15
IMPORTS | 1 | 7 | 17
EQ | 22 | 
       EXP32_.EXP  =  a<0> & !b<0> & a<1> & b<1> & c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<1> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & !b<1> & c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !c<3> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_18
	# a<0> & !b<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & b<1> & !c<3> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 7 | 17 | EXP33_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 7 | 16
INPUTS | 7 | a<0>  | b<0>  | a<1>  | b<1>  | c<3>  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
INPUTMC | 3 | 5 | 9 | 5 | 17 | 3 | 17
INPUTP | 4 | 77 | 66 | 74 | 64
EXPORTS | 1 | 7 | 16
EQ | 9 | 
       EXP33_.EXP  =  a<0> & !b<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & b<1> & !c<3> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

PIN | a<0> | 64 | 0 | N/A | 77 | 33 | 3 | 0 | 1 | 15 | 5 | 9 | 5 | 7 | 6 | 15 | 7 | 15 | 5 | 1 | 4 | 16 | 5 | 17 | 4 | 0 | 0 | 16 | 2 | 17 | 0 | 15 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 1 | 17 | 3 | 1 | 4 | 1 | 4 | 2 | 4 | 17 | 5 | 0 | 5 | 2 | 5 | 3 | 5 | 16 | 6 | 13 | 6 | 14 | 6 | 17 | 7 | 13 | 7 | 14 | 7 | 16 | 7 | 17
PIN | b<0> | 64 | 0 | N/A | 66 | 33 | 3 | 0 | 1 | 15 | 5 | 9 | 5 | 7 | 6 | 15 | 7 | 15 | 5 | 1 | 4 | 16 | 5 | 17 | 4 | 0 | 0 | 16 | 2 | 17 | 0 | 15 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 1 | 17 | 3 | 1 | 4 | 1 | 4 | 2 | 4 | 17 | 5 | 0 | 5 | 2 | 5 | 3 | 5 | 16 | 6 | 13 | 6 | 14 | 6 | 17 | 7 | 13 | 7 | 14 | 7 | 16 | 7 | 17
PIN | a<1> | 64 | 0 | N/A | 74 | 31 | 1 | 17 | 1 | 15 | 5 | 9 | 5 | 7 | 6 | 15 | 7 | 15 | 5 | 15 | 4 | 16 | 5 | 17 | 4 | 0 | 0 | 16 | 2 | 17 | 5 | 16 | 0 | 14 | 0 | 15 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 3 | 2 | 4 | 1 | 4 | 2 | 4 | 17 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 7 | 13 | 7 | 14 | 7 | 16 | 7 | 17
PIN | b<1> | 64 | 0 | N/A | 64 | 31 | 1 | 17 | 1 | 15 | 5 | 9 | 5 | 7 | 6 | 15 | 7 | 15 | 5 | 15 | 4 | 16 | 5 | 17 | 4 | 0 | 0 | 16 | 2 | 17 | 5 | 16 | 0 | 14 | 0 | 15 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 3 | 2 | 4 | 1 | 4 | 2 | 4 | 17 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 7 | 13 | 7 | 14 | 7 | 16 | 7 | 17
PIN | a<2> | 64 | 0 | N/A | 72 | 29 | 1 | 15 | 5 | 9 | 5 | 7 | 6 | 15 | 5 | 1 | 5 | 14 | 5 | 17 | 4 | 0 | 0 | 16 | 2 | 17 | 5 | 16 | 0 | 14 | 0 | 15 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 1 | 17 | 4 | 1 | 4 | 2 | 4 | 16 | 4 | 17 | 5 | 0 | 5 | 2 | 5 | 3 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17
PIN | b<2> | 64 | 0 | N/A | 63 | 27 | 1 | 15 | 5 | 9 | 5 | 7 | 6 | 15 | 5 | 1 | 5 | 14 | 5 | 17 | 4 | 0 | 0 | 16 | 5 | 16 | 0 | 14 | 0 | 15 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 1 | 17 | 4 | 1 | 4 | 2 | 4 | 17 | 5 | 0 | 5 | 2 | 5 | 3 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17
PIN | a<3> | 64 | 0 | N/A | 69 | 4 | 3 | 0 | 3 | 17 | 3 | 1 | 3 | 2
PIN | b<3> | 64 | 0 | N/A | 62 | 4 | 3 | 0 | 3 | 17 | 3 | 1 | 3 | 2
PIN | c<1> | 536871040 | 0 | N/A | 133
PIN | c<2> | 536871040 | 0 | N/A | 130
PIN | c<3> | 536871040 | 0 | N/A | 129
PIN | c<4> | 536871040 | 0 | N/A | 127
PIN | c<5> | 536871040 | 0 | N/A | 124
PIN | c<6> | 536871040 | 0 | N/A | 119
PIN | c<7> | 536871040 | 0 | N/A | 118
PIN | c<0> | 536871040 | 0 | N/A | 134
PIN | en | 536871040 | 0 | N/A | 147
1234

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