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📄 sub.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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1234 
INPUTMC | 1 | 1 | 15
EQ | 1 | 
   c<2> = c<2>_BUFR;

MACROCELL | 0 | 14 | EXP12_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 0 | 15
INPUTS | 5 | a<1>  | b<1>  | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
INPUTMC | 1 | 3 | 17
INPUTP | 4 | 74 | 64 | 72 | 63
EXPORTS | 1 | 0 | 15
EQ | 2 | 
       EXP12_.EXP  =  a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 0 | 15 | EXP13_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 0 | 16
INPUTS | 8 | a<0>  | b<0>  | a<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | a<1>  | b<2>  | b<1>  | EXP12_.EXP
INPUTMC | 2 | 3 | 17 | 0 | 14
INPUTP | 6 | 77 | 66 | 72 | 74 | 63 | 64
EXPORTS | 1 | 0 | 16
IMPORTS | 1 | 0 | 14
EQ | 13 | 
       EXP13_.EXP  =  !a<0> & b<0> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB1_15
	# a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 0 | 17 | EXP14_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 0 | 16
INPUTS | 7 | a<0>  | b<0>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | a<2>  | a<1>  | b<1>
INPUTMC | 1 | 3 | 17
INPUTP | 6 | 77 | 66 | 63 | 72 | 74 | 64
EXPORTS | 1 | 0 | 16
EQ | 10 | 
       EXP14_.EXP  =  !a<0> & b<0> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & b<1> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & !b<1> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 1 | 13 | EXP15_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 1 | 14
INPUTS | 7 | a<0>  | b<0>  | a<1>  | b<1>  | a<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | b<2>
INPUTMC | 1 | 3 | 17
INPUTP | 6 | 77 | 66 | 74 | 64 | 72 | 63
EXPORTS | 1 | 1 | 14
EQ | 8 | 
       EXP15_.EXP  =  a<0> & !b<0> & !a<1> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 1 | 14 | EXP16_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 1 | 15
INPUTS | 8 | a<0>  | b<0>  | a<1>  | b<1>  | a<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | b<2>  | EXP15_.EXP
INPUTMC | 2 | 3 | 17 | 1 | 13
INPUTP | 6 | 77 | 66 | 74 | 64 | 72 | 63
EXPORTS | 1 | 1 | 15
IMPORTS | 1 | 1 | 13
EQ | 19 | 
       EXP16_.EXP  =  a<0> & !b<0> & a<1> & b<1> & !a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<1> & a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & !b<1> & !a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !b<1> & a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB2_14
	# a<0> & !b<0> & !a<1> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 1 | 16 | EXP17_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 1 | 15
INPUTS | 8 | a<1>  | b<1>  | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | a<0>  | b<0>  | EXP18_.EXP
INPUTMC | 2 | 3 | 17 | 1 | 17
INPUTP | 6 | 74 | 64 | 72 | 63 | 77 | 66
EXPORTS | 1 | 1 | 15
IMPORTS | 1 | 1 | 17
EQ | 21 | 
       EXP17_.EXP  =  a<1> & !b<1> & a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & !b<1> & !a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & b<1> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB2_18
	# !a<0> & b<0> & !a<1> & !b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & !b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & !b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 1 | 17 | EXP18_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 1 | 16
INPUTS | 7 | a<0>  | b<0>  | a<1>  | b<1>  | a<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | b<2>
INPUTMC | 1 | 3 | 17
INPUTP | 6 | 77 | 66 | 74 | 64 | 72 | 63
EXPORTS | 1 | 1 | 16
EQ | 10 | 
       EXP18_.EXP  =  !a<0> & b<0> & !a<1> & !b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & !b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & !b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 3 | 1 | EXP19_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 0
INPUTS | 11 | a<0>  | b<0>  | c<3>  | c<4>  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | a<3>  | b<3>  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | EXP20_.EXP
INPUTMC | 7 | 5 | 9 | 5 | 7 | 5 | 15 | 4 | 16 | 5 | 14 | 5 | 17 | 3 | 2
INPUTP | 4 | 77 | 66 | 69 | 62
EXPORTS | 1 | 3 | 0
IMPORTS | 1 | 3 | 2
EQ | 25 | 
       EXP19_.EXP  =  a<0> & !b<0> & !c<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & !c<3> & c<4> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & !c<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# b<0> & !c<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<3> & !b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
;Imported pterms FB4_3
	# a<1> & !b<1> & a<3> & b<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<1> & !b<1> & !a<3> & !b<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<3> & !b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<3> & b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2

MACROCELL | 3 | 2 | EXP20_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 1
INPUTS | 8 | a<1>  | b<1>  | a<3>  | b<3>  | c<4>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
INPUTMC | 4 | 5 | 7 | 5 | 14 | 4 | 16 | 5 | 17
INPUTP | 4 | 74 | 64 | 69 | 62
EXPORTS | 1 | 3 | 1
EQ | 10 | 
       EXP20_.EXP  =  a<1> & !b<1> & a<3> & b<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<1> & !b<1> & !a<3> & !b<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<3> & !b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<3> & b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2

MACROCELL | 4 | 1 | EXP21_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 4 | 0
INPUTS | 9 | a<0>  | b<0>  | a<1>  | b<1>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | EXP22_.EXP
INPUTMC | 3 | 5 | 14 | 3 | 17 | 4 | 2
INPUTP | 6 | 77 | 66 | 74 | 64 | 72 | 63
EXPORTS | 1 | 4 | 0
IMPORTS | 1 | 4 | 2
EQ | 25 | 
       EXP21_.EXP  =  a<0> & !b<0> & a<1> & !b<1> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & !a<1> & b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !a<1> & b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# b<0> & !a<1> & b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# b<0> & !a<1> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB5_3
	# a<0> & b<0> & a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & b<0> & !a<1> & !b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & b<0> & !a<1> & !b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !b<0> & a<1> & b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !b<0> & a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 4 | 2 | EXP22_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 4 | 1
INPUTS | 8 | a<0>  | b<0>  | a<1>  | b<1>  | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
INPUTMC | 2 | 3 | 17 | 5 | 14
INPUTP | 6 | 77 | 66 | 74 | 64 | 72 | 63
EXPORTS | 1 | 4 | 1
EQ | 12 | 
       EXP22_.EXP  =  a<0> & b<0> & a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & b<0> & !a<1> & !b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & b<0> & !a<1> & !b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !b<0> & a<1> & b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !b<0> & a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 4 | 17 | EXP23_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 4 | 0
INPUTS | 9 | a<0>  | b<0>  | b<1>  | a<2>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | b<2>  | a<1>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400.EXP
INPUTMC | 3 | 5 | 14 | 3 | 17 | 4 | 16
INPUTP | 6 | 77 | 66 | 64 | 72 | 63 | 74
EXPORTS | 1 | 4 | 0
IMPORTS | 1 | 4 | 16
EQ | 16 | 
       EXP23_.EXP  =  !a<0> & b<0> & !b<1> & !a<2> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & b<0> & !b<1> & b<2> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & a<1> & !b<1> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# b<0> & a<1> & !b<1> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D &
1234

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