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📄 sub.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_1
	# a<0> & !b<0> & !c<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# c<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<2> & b<2> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & !b<2> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_3
	# a<2> & !b<2> & c<4> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<2> & b<2> & c<4> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_4
	# !a<0> & b<0> & !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<2> & !b<2> & !c<3> & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & b<2> & !c<3> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 5 | 10 | c_0_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   c<0> = Vcc;

MACROCELL | 3 | 10 | en_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   en = Gnd;

MACROCELL | 5 | 15 | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 7 | 3 | 0 | 5 | 1 | 3 | 1 | 3 | 17 | 5 | 0 | 5 | 2 | 5 | 3
INPUTS | 2 | b<1>  | a<1>
INPUTP | 2 | 64 | 74
EQ | 2 | 
   !Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D = b<1>
	$ a<1>;

MACROCELL | 4 | 16 | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400
ATTRIBUTES | 133888 | 0
OUTPUTMC | 8 | 3 | 0 | 5 | 1 | 3 | 1 | 3 | 2 | 3 | 17 | 5 | 2 | 5 | 3 | 4 | 17
INPUTS | 7 | a<0>  | b<0>  | a<1>  | b<1>  | a<2>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
INPUTMC | 2 | 5 | 14 | 3 | 17
INPUTP | 5 | 77 | 66 | 74 | 64 | 72
EXPORTS | 1 | 4 | 17
EQ | 6 | 
   $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 = !a<1> & b<1>
	# !a<0> & b<0> & !a<1>
	# !a<0> & b<0> & b<1>;
    $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400.EXP  =  a<0> & b<0> & a<1> & b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 5 | 14 | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 14 | 3 | 0 | 2 | 17 | 7 | 15 | 4 | 0 | 3 | 1 | 3 | 2 | 3 | 17 | 4 | 1 | 4 | 2 | 4 | 16 | 4 | 17 | 7 | 13 | 7 | 14 | 7 | 16
INPUTS | 2 | b<2>  | a<2>
INPUTP | 2 | 63 | 72
EQ | 2 | 
   !Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D = b<2>
	$ a<2>;

MACROCELL | 5 | 17 | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 13 | 3 | 0 | 6 | 15 | 7 | 14 | 3 | 1 | 3 | 2 | 3 | 17 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 7 | 13 | 7 | 16 | 7 | 17
INPUTS | 7 | a<1>  | b<1>  | a<2>  | a<0>  | b<0>  | b<2>  | $OpTx$DEC_c_3_OBUF$3.EXP
INPUTMC | 1 | 5 | 16
INPUTP | 6 | 74 | 64 | 72 | 77 | 66 | 63
IMPORTS | 1 | 5 | 16
EQ | 8 | 
   Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 = !a<2> & b<2>
	# !a<1> & b<1> & !a<2>
	# !a<1> & b<1> & b<2>
	# !a<0> & b<0> & !a<1> & !a<2>
	# !a<0> & b<0> & b<1> & !a<2>
;Imported pterms FB6_17
	# !a<0> & b<0> & !a<1> & b<2>
	# !a<0> & b<0> & b<1> & b<2>;

MACROCELL | 3 | 17 | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 30 | 1 | 15 | 5 | 16 | 5 | 7 | 6 | 15 | 7 | 14 | 5 | 1 | 1 | 17 | 0 | 16 | 2 | 17 | 0 | 14 | 0 | 15 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 4 | 1 | 4 | 2 | 4 | 16 | 4 | 17 | 5 | 0 | 5 | 2 | 5 | 3 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17 | 7 | 13 | 7 | 16 | 7 | 17 | 3 | 0
INPUTS | 8 | b<3>  | a<3>  | c<4>  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | c<3>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
INPUTMC | 6 | 5 | 7 | 4 | 16 | 5 | 17 | 5 | 9 | 5 | 14 | 5 | 15
INPUTP | 2 | 62 | 69
EXPORTS | 1 | 3 | 0
EQ | 9 | 
   !Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D = b<3>
	$ a<3>;
    Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D.EXP  =  a<3> & b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<3> & !b<3> & c<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<3> & !b<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2

MACROCELL | 4 | 0 | $OpTx$DEC_c_4_OBUF$0
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 2 | 17
INPUTS | 9 | a<0>  | b<0>  | a<1>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | b<1>  | a<2>  | b<2>  | EXP21_.EXP  | EXP23_.EXP
INPUTMC | 3 | 5 | 14 | 4 | 1 | 4 | 17
INPUTP | 6 | 77 | 66 | 74 | 64 | 72 | 63
IMPORTS | 2 | 4 | 1 | 4 | 17
EQ | 53 | 
   $OpTx$DEC_c_4_OBUF$0 = a<0> & !b<0> & !a<1> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<0> & !b<0> & b<1> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & b<0> & a<1> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<1> & b<1> & !a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
;Imported pterms FB5_2
	# a<0> & !b<0> & a<1> & !b<1> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & !a<1> & b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !a<1> & b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# b<0> & !a<1> & b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# b<0> & !a<1> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB5_3
	# a<0> & b<0> & a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & b<0> & !a<1> & !b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & b<0> & !a<1> & !b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !b<0> & a<1> & b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !b<0> & a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB5_18
	# !a<0> & b<0> & !b<1> & !a<2> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & b<0> & !b<1> & b<2> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & a<1> & !b<1> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# b<0> & a<1> & !b<1> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & !b<1> & !a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
;Imported pterms FB5_17
	# a<0> & b<0> & a<1> & b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 0 | 16 | $OpTx$DEC_c_3_OBUF$1
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 5 | 16
INPUTS | 9 | a<0>  | b<0>  | a<1>  | b<1>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | a<2>  | EXP13_.EXP  | EXP14_.EXP
INPUTMC | 3 | 3 | 17 | 0 | 15 | 0 | 17
INPUTP | 6 | 77 | 66 | 74 | 64 | 63 | 72
IMPORTS | 2 | 0 | 15 | 0 | 17
EQ | 32 | 
   $OpTx$DEC_c_3_OBUF$1 = a<0> & !b<0> & !a<1> & !b<1> & a<2> & b<2>
	# a<0> & !b<0> & !a<1> & !b<1> & !a<2> & !b<2>
	# !a<0> & b<0> & a<1> & !b<1> & a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & !b<1> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & a<2> & !b<2>
;Imported pterms FB1_16
	# !a<0> & b<0> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB1_15
	# a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB1_18
	# !a<0> & b<0> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & b<1> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & !b<1> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 2 | 17 | $OpTx$DEC_c_4_OBUF$2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 5 | 7
INPUTS | 8 | $OpTx$DEC_c_4_OBUF$0  | a<0>  | b<0>  | a<1>  | b<1>  | a<2>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
INPUTMC | 3 | 4 | 0 | 5 | 14 | 3 | 17
INPUTP | 5 | 77 | 66 | 74 | 64 | 72
EQ | 4 | 
   $OpTx$DEC_c_4_OBUF$2 = $OpTx$DEC_c_4_OBUF$0
	# !a<0> & !b<0> & !a<1> & !b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 5 | 16 | $OpTx$DEC_c_3_OBUF$3
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 5 | 9 | 5 | 17
INPUTS | 8 | $OpTx$DEC_c_3_OBUF$1  | a<1>  | b<1>  | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | a<0>  | b<0>
INPUTMC | 2 | 0 | 16 | 3 | 17
INPUTP | 6 | 74 | 64 | 72 | 63 | 77 | 66
EXPORTS | 1 | 5 | 17
EQ | 5 | 
   $OpTx$DEC_c_3_OBUF$3 = $OpTx$DEC_c_3_OBUF$1
	# !a<1> & !b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;
    $OpTx$DEC_c_3_OBUF$3.EXP  =  !a<0> & b<0> & !a<1> & b<2>
	# !a<0> & b<0> & b<1> & b<2>

MACROCELL | 5 | 3 | _10_
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 5 | 2
INPUTS | 9 | c<5>_BUFR  | a<0>  | b<0>  | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | c<3>  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400
INPUTMC | 5 | 6 | 15 | 5 | 15 | 3 | 17 | 5 | 9 | 4 | 16
INPUTP | 4 | 77 | 66 | 72 | 63
EXPORTS | 1 | 5 | 2
EQ | 14 | 
   c<5> = c<5>_BUFR;
    _10_.EXP  =  !a<0> & b<0> & !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<2> & !b<2> & !c<3> & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & b<2> & !c<3> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 5 | 8 | _11_
ATTRIBUTES | 264962 | 0
INPUTS | 1 | c<2>_BUFR
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