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📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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MDF Database:  version 1.0
MDF_INFO | sub | XC95144XL-10-TQ144
MACROCELL | 3 | 0 | c_1_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 12 | c<3>  | c<4>  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | a<0>  | b<0>  | a<3>  | b<3>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | EXP19_.EXP  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D.EXP
INPUTMC | 8 | 5 | 9 | 5 | 7 | 5 | 15 | 4 | 16 | 5 | 14 | 5 | 17 | 3 | 1 | 3 | 17
INPUTP | 4 | 77 | 66 | 69 | 62
IMPORTS | 2 | 3 | 1 | 3 | 17
EQ | 46 | 
   c<1> = a<0> & c<3> & c<4> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !b<0> & c<3> & c<4> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# c<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400
	# a<3> & b<3> & c<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<3> & b<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
;Imported pterms FB4_2
	# a<0> & !b<0> & !c<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & !c<3> & c<4> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & !c<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# b<0> & !c<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<3> & !b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
;Imported pterms FB4_3
	# a<1> & !b<1> & a<3> & b<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<1> & !b<1> & !a<3> & !b<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<3> & !b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<3> & b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
;Imported pterms FB4_18
	# a<3> & b<3> & c<4> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<3> & !b<3> & c<3> & c<4> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<3> & !b<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2;

MACROCELL | 1 | 15 | c<2>_BUFR.MC
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 5 | 8
INPUTS | 9 | a<0>  | b<0>  | a<1>  | b<1>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | a<2>  | EXP16_.EXP  | EXP17_.EXP
INPUTMC | 3 | 3 | 17 | 1 | 14 | 1 | 16
INPUTP | 6 | 77 | 66 | 74 | 64 | 63 | 72
IMPORTS | 2 | 1 | 14 | 1 | 16
EQ | 52 | 
   c<2>_BUFR = !a<0> & b<0> & a<1> & !b<1> & !a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & b<1> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB2_15
	# a<0> & !b<0> & a<1> & b<1> & !a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<1> & a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & !b<1> & !a<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !b<1> & a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB2_14
	# a<0> & !b<0> & !a<1> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB2_17
	# a<1> & !b<1> & a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & !b<1> & !a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & b<1> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB2_18
	# !a<0> & b<0> & !a<1> & !b<1> & !a<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & !b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & !b<1> & a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 5 | 9 | c_3_OBUF
ATTRIBUTES | 396034 | 0
OUTPUTMC | 15 | 3 | 0 | 6 | 14 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 17 | 5 | 0 | 5 | 3 | 6 | 13 | 6 | 16 | 6 | 17 | 7 | 13 | 7 | 14 | 7 | 16 | 7 | 17
INPUTS | 7 | a<0>  | b<0>  | a<1>  | b<1>  | a<2>  | b<2>  | $OpTx$DEC_c_3_OBUF$3
INPUTMC | 1 | 5 | 16
INPUTP | 6 | 77 | 66 | 74 | 64 | 72 | 63
EQ | 2 | 
   c<3> = $OpTx$DEC_c_3_OBUF$3
	# !a<0> & b<0> & !a<1> & b<1> & !a<2> & b<2>;

MACROCELL | 5 | 7 | c_4_OBUF
ATTRIBUTES | 396034 | 0
OUTPUTMC | 6 | 3 | 0 | 5 | 0 | 3 | 1 | 3 | 2 | 3 | 17 | 5 | 2
INPUTS | 8 | a<0>  | b<0>  | a<1>  | b<1>  | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | $OpTx$DEC_c_4_OBUF$2
INPUTMC | 2 | 3 | 17 | 2 | 17
INPUTP | 6 | 77 | 66 | 74 | 64 | 72 | 63
EQ | 3 | 
   c<4> = $OpTx$DEC_c_4_OBUF$2
	# !a<0> & !b<0> & !a<1> & !b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 6 | 15 | c<5>_BUFR.MC
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 5 | 3
INPUTS | 10 | a<0>  | b<0>  | b<1>  | a<2>  | b<2>  | a<1>  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | EXP27_.EXP  | EXP28_.EXP
INPUTMC | 4 | 5 | 17 | 3 | 17 | 6 | 14 | 6 | 16
INPUTP | 6 | 77 | 66 | 64 | 72 | 63 | 74
IMPORTS | 2 | 6 | 14 | 6 | 16
EQ | 45 | 
   !c<5>_BUFR = !a<0> & b<0> & !a<1> & a<2> & !b<2>
	# !a<0> & b<0> & !a<1> & !a<2> & b<2>
	# !a<0> & b<0> & b<1> & a<2> & !b<2>
	# !a<0> & b<0> & b<1> & !a<2> & b<2>
	# a<1> & a<2> & !b<2> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB7_15
	# a<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & !a<2> & b<2> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<0> & b<0> & a<1> & !b<1> & !c<3>
;Imported pterms FB7_14
	# !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & a<1> & !b<1> & c<3>
	# !a<0> & b<0> & !a<1> & b<1>
	# !a<1> & b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB7_17
	# !a<1> & b<1> & c<3>
	# a<2> & b<2> & c<3>
	# a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<2> & !b<2> & c<3>
	# !a<1> & !b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB7_18
	# !b<0> & a<1> & !b<1> & c<3>
	# a<0> & !b<0> & a<1> & b<1> & !c<3>
	# a<0> & !b<0> & !a<1> & !b<1> & !c<3>
	# !a<1> & b<1> & a<2> & !b<2> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & b<1> & !a<2> & b<2> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 7 | 15 | c_6_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 8 | a<0>  | b<0>  | b<1>  | c<3>  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | a<1>  | EXP31_.EXP  | EXP32_.EXP
INPUTMC | 4 | 5 | 9 | 5 | 14 | 7 | 14 | 7 | 16
INPUTP | 4 | 77 | 66 | 64 | 74
IMPORTS | 2 | 7 | 14 | 7 | 16
EQ | 59 | 
   c<6> = a<0> & b<0> & a<1> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<0> & b<0> & !b<1> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & !b<0> & a<1> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & !b<0> & !b<1> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !b<0> & a<1> & !b<1> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
;Imported pterms FB8_15
	# a<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# a<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & !b<1> & c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !b<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !b<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_14
	# !a<0> & b<0> & a<1> & b<1> & !c<3> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_17
	# a<0> & !b<0> & a<1> & b<1> & c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<1> & !c<3> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & !b<1> & c<3> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !c<3> & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !c<3> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_18
	# a<0> & !b<0> & !a<1> & b<1> & !c<3> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & b<1> & !c<3> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 5 | 1 | c_7_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 10 | a<0>  | a<2>  | b<2>  | c<3>  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | b<0>  | EXP24_.EXP  | EXP25_.EXP
INPUTMC | 6 | 5 | 9 | 5 | 15 | 4 | 16 | 3 | 17 | 5 | 0 | 5 | 2
INPUTP | 4 | 77 | 72 | 63 | 66
IMPORTS | 2 | 5 | 0 | 5 | 2
EQ | 60 | 
   c<7> = a<0> & !b<0> & b<2> & !c<3> & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !b<2> & !c<3> & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & a<2> & !b<2> & !c<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !a<2> & b<2> & !c<3> &
1234

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