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2 0 \/3 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 5: a<0> 9: b<1>
2: Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D 6: a<1> 10: b<3>
3: Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D 7: a<3> 11: c<3>
4: Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 8: b<0> 12: c<4>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
c<1> XXXXXXXXXXXX............................ 12
en ........................................ 0
Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
......X..X.............................. 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 8/46
Number of signals used by logic mapping into function block: 8
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
$OpTx$DEC_c_4_OBUF$0
21 16<- 0 0 FB5_1 (b) (b)
(unused) 0 0 /\5 0 FB5_2 52 I/O (b)
(unused) 0 0 /\5 0 FB5_3 59 I/O I
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 53 I/O
(unused) 0 0 0 5 FB5_6 54 I/O
(unused) 0 0 0 5 FB5_7 66 I/O I
(unused) 0 0 0 5 FB5_8 56 I/O I
(unused) 0 0 0 5 FB5_9 57 I/O I
(unused) 0 0 0 5 FB5_10 68 I/O
(unused) 0 0 0 5 FB5_11 58 I/O I
(unused) 0 0 0 5 FB5_12 60 I/O
(unused) 0 0 0 5 FB5_13 70 I/O
(unused) 0 0 0 5 FB5_14 61 I/O I
(unused) 0 0 0 5 FB5_15 64 I/O I
(unused) 0 0 0 5 FB5_16 (b)
$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400
3 0 \/1 1 FB5_17 69 I/O I
(unused) 0 0 \/5 0 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D 4: a<1> 7: b<1>
2: Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D 5: a<2> 8: b<2>
3: a<0> 6: b<0>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
$OpTx$DEC_c_4_OBUF$0
XXXXXXXX................................ 8
$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400
..XX.XX................................. 4
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/5 0 FB6_1 (b) (b)
c<7> 19 14<- 0 0 FB6_2 106 I/O O
(unused) 0 0 /\5 0 FB6_3 (b) (b)
c<5> 1 0 /\4 0 FB6_4 111 I/O O
(unused) 0 0 0 5 FB6_5 110 I/O
(unused) 0 0 0 5 FB6_6 112 I/O
(unused) 0 0 0 5 FB6_7 (b)
c<4> 2 0 0 3 FB6_8 113 I/O O
c<2> 1 0 0 4 FB6_9 116 I/O O
c<3> 2 0 0 3 FB6_10 115 I/O O
c<0> 0 0 0 5 FB6_11 119 I/O O
(unused) 0 0 0 5 FB6_12 120 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 121 I/O
Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
2 0 0 3 FB6_15 124 I/O (b)
Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
2 0 0 3 FB6_16 117 I/O (b)
$OpTx$DEC_c_3_OBUF$3
2 0 \/2 1 FB6_17 125 I/O (b)
Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
7 2<- 0 0 FB6_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$DEC_c_3_OBUF$1 7: a<0> 12: b<2>
2: $OpTx$DEC_c_3_OBUF$3 8: a<1> 13: c<2>_BUFR
3: $OpTx$DEC_c_4_OBUF$2 9: a<2> 14: c<3>
4: $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 10: b<0> 15: c<4>
5: Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D 11: b<1> 16: c<5>_BUFR
6: Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
c<7> ...XXXX.XX.X.XX......................... 9
c<5> ...............X........................ 1
c<4> ..X..XXXXXXX............................ 8
c<2> ............X........................... 1
c<3> .X....XXXXXX............................ 7
c<0> ........................................ 0
Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
........X..X............................ 2
Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
.......X..X............................. 2
$OpTx$DEC_c_3_OBUF$3
X....X.XX.XX............................ 6
Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
......XXXXXX............................ 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 9/45
Number of signals used by logic mapping into function block: 9
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 71 I/O
(unused) 0 0 0 5 FB7_3 75 I/O
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 74 I/O
(unused) 0 0 0 5 FB7_6 76 I/O
(unused) 0 0 0 5 FB7_7 77 I/O
(unused) 0 0 0 5 FB7_8 78 I/O
(unused) 0 0 0 5 FB7_9 80 I/O
(unused) 0 0 0 5 FB7_10 79 I/O
(unused) 0 0 0 5 FB7_11 82 I/O
(unused) 0 0 0 5 FB7_12 85 I/O
(unused) 0 0 0 5 FB7_13 81 I/O
(unused) 0 0 \/4 1 FB7_14 86 I/O (b)
(unused) 0 0 \/5 0 FB7_15 87 I/O (b)
c<5>_BUFR 24 19<- 0 0 FB7_16 83 I/O (b)
(unused) 0 0 /\5 0 FB7_17 88 I/O (b)
(unused) 0 0 /\5 0 FB7_18 (b) (b)
Signals Used by Logic in Function Block
1: Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D 4: a<1> 7: b<1>
2: Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 5: a<2> 8: b<2>
3: a<0> 6: b<0> 9: c<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
c<5>_BUFR XXXXXXXXX............................... 9
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 8/46
Number of signals used by logic mapping into function block: 8
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
(unused) 0 0 0 5 FB8_2 91 I/O
(unused) 0 0 0 5 FB8_3 95 I/O
(unused) 0 0 0 5 FB8_4 97 I/O
(unused) 0 0 0 5 FB8_5 92 I/O
(unused) 0 0 0 5 FB8_6 93 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 94 I/O
(unused) 0 0 0 5 FB8_9 96 I/O
(unused) 0 0 0 5 FB8_10 101 I/O
(unused) 0 0 0 5 FB8_11 98 I/O
(unused) 0 0 0 5 FB8_12 100 I/O
(unused) 0 0 0 5 FB8_13 103 I/O
(unused) 0 0 \/4 1 FB8_14 102 I/O (b)
(unused) 0 0 \/5 0 FB8_15 104 I/O (b)
c<6> 22 17<- 0 0 FB8_16 107 I/O O
(unused) 0 0 /\5 0 FB8_17 105 I/O (b)
(unused) 0 0 /\3 2 FB8_18 (b) (b)
Signals Used by Logic in Function Block
1: Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D 4: a<0> 7: b<1>
2: Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D 5: a<1> 8: c<3>
3: Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 6: b<0>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
c<6> XXXXXXXX................................ 8
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
assign $OpTx$DEC_c_3_OBUF$1 = ((EXP13_.EXP)
|| (EXP14_.EXP)
|| (a[0] && !b[0] && !a[1] && !b[1] && a[2] && b[2])
|| (a[0] && !b[0] && !a[1] && !b[1] && !a[2] && !b[2])
|| (!a[0] && b[0] && a[1] && !b[1] && a[2] &&
Msub_c_tmp_Mxor_Result[3]__n0002[0]/Msub_c_tmp_Mxor_Result[3]__n0002[0]_D)
|| (!a[0] && b[0] && a[1] && !b[1] && !b[2] &&
Msub_c_tmp_Mxor_Result[3]__n0002[0]/Msub_c_tmp_Mxor_Result[3]__n0002[0]_D)
|| (!a[0] && b[0] && !a[1] && b[1] && a[2] && !b[2]));
assign $OpTx$DEC_c_3_OBUF$3 = (($OpTx$DEC_c_3_OBUF$1)
|| (!a[1] && !b[1] && !a[2] && b[2] &&
!Msub_c_tmp_Mxor_Result[3]__n0002[0]/Msub_c_tmp_Mxor_Result[3]__n0002[0]_D));
assign $OpTx$DEC_c_4_OBUF$0 = ((EXP21_.EXP)
|| (EXP23_.EXP)
|| (a[0] && !b[0] && !a[1] &&
Msub_c_tmp_Mxor_Result[2]__n0002[0]/Msub_c_tmp_Mxor_Result[2]__n0002[0]_D)
|| (a[0] && !b[0] && b[1] &&
Msub_c_tmp_Mxor_Result[2]__n0002[0]/Msub_c_tmp_Mxor_Result[2]__n0002[0]_D)
|| (!a[0] && b[0] && a[1] &&
Msub_c_tmp_Mxor_Result[2]__n0002[0]/Msub_c_tmp_Mxor_Result[2]__n0002[0]_D)
|| (!a[0] && b[0] && !a[1] && b[1] &&
!Msub_c_tmp_Mxor_Result[2]__n0002[0]/Msub_c_tmp_Mxor_Result[2]__n0002[0]_D)
|| (a[1] && b[1] && !a[2] && b[2] &&
Msub_c_tmp_Mxor_Result[2]__n0002[0]/Msub_c_tmp_Mxor_Result[2]__n0002[0]_D));
assign $OpTx$DEC_c_4_OBUF$2 = (($OpTx$DEC_c_4_OBUF$0)
|| (!a[0] && !b[0] && !a[1] && !b[1] && a[2] &&
!Msub_c_tmp_Mxor_Result[2]__n0002[0]/Msub_c_tmp_Mxor_Result[2]__n0002[0]_D &&
Msub_c_tmp_Mxor_Result[3]__n0002[0]/Msub_c_tmp_Mxor_Result[3]__n0002[0]_D));
assign $OpTx$Msub_c_tmp__n0016[0]/Msub_c_tmp__n0016[0]_D2_INV$400 = ((!a[1] && b[1])
|| (!a[0] && b[0] && !a[1])
|| (!a[0] && b[0] && b[1]));
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