📄 encode.rpt
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Signals Used by Logic in Function Block
1: a<1> 4: a<4> 7: a<7>
2: a<2> 5: a<5> 8: a<8>
3: a<3> 6: a<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
c<7> XXXXXXXX................................ 8
c<5> .XXXXXXX................................ 7
c<4> XXXXXXXX................................ 8
c<2> XXXXXXXX................................ 8
c<3> XXXXXXXX................................ 8
c<0> ........................................ 0
en<3> ........................................ 0
en<4> ........................................ 0
en<5> ........................................ 0
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB7_1 (b)
(unused) 0 0 0 5 FB7_2 71 I/O
(unused) 0 0 0 5 FB7_3 75 I/O
(unused) 0 0 0 5 FB7_4 (b)
(unused) 0 0 0 5 FB7_5 74 I/O
(unused) 0 0 0 5 FB7_6 76 I/O
(unused) 0 0 0 5 FB7_7 77 I/O
(unused) 0 0 0 5 FB7_8 78 I/O
(unused) 0 0 0 5 FB7_9 80 I/O
(unused) 0 0 0 5 FB7_10 79 I/O
(unused) 0 0 0 5 FB7_11 82 I/O
(unused) 0 0 0 5 FB7_12 85 I/O
(unused) 0 0 0 5 FB7_13 81 I/O
(unused) 0 0 0 5 FB7_14 86 I/O
(unused) 0 0 0 5 FB7_15 87 I/O
(unused) 0 0 0 5 FB7_16 83 I/O
(unused) 0 0 0 5 FB7_17 88 I/O
(unused) 0 0 0 5 FB7_18 (b)
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 4/50
Number of signals used by logic mapping into function block: 4
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
(unused) 0 0 0 5 FB8_2 91 I/O
(unused) 0 0 0 5 FB8_3 95 I/O
(unused) 0 0 0 5 FB8_4 97 I/O
(unused) 0 0 0 5 FB8_5 92 I/O
(unused) 0 0 0 5 FB8_6 93 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 94 I/O
(unused) 0 0 0 5 FB8_9 96 I/O
(unused) 0 0 0 5 FB8_10 101 I/O
(unused) 0 0 0 5 FB8_11 98 I/O
(unused) 0 0 0 5 FB8_12 100 I/O
(unused) 0 0 0 5 FB8_13 103 I/O
(unused) 0 0 0 5 FB8_14 102 I/O
(unused) 0 0 0 5 FB8_15 104 I/O
c<6> 2 0 0 3 FB8_16 107 I/O O
(unused) 0 0 0 5 FB8_17 105 I/O
(unused) 0 0 0 5 FB8_18 (b)
Signals Used by Logic in Function Block
1: a<5> 3: a<7> 4: a<8>
2: a<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
c<6> XXXX.................................... 4
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
assign c[0] = 1'b1;
assign c[1] = ((!a[8] && a[7])
|| (!a[2] && !a[8] && !a[6] && !a[5] && !a[4] && !a[3]));
assign c[2] = ((!a[8] && a[7])
|| (a[2] && !a[8] && !a[6] && !a[5] && !a[4])
|| (!a[8] && !a[6] && !a[5] && !a[4] && a[3])
|| (!a[8] && !a[6] && !a[5] && !a[4] && a[1]));
assign c[3] = !(((a[8])
|| (!a[7] && a[6])
|| (a[2] && !a[7] && !a[5] && !a[4] && !a[3])
|| (!a[7] && !a[5] && !a[4] && !a[3] && !a[1])));
assign c[4] = ((!a[8] && a[7])
|| (!a[8] && !a[6] && !a[5] && a[4])
|| (!a[2] && !a[8] && !a[6] && !a[5] && !a[3] && a[1]));
assign c[5] = (a[2] && !a[8] && !a[7] && !a[6] && !a[5] && !a[4] &&
!a[3]);
assign c[6] = ((!a[8] && !a[7] && a[6])
|| (!a[8] && !a[7] && a[5]));
assign c[7] = ((!a[8] && !a[7] && !a[6] && !a[5] && a[4])
|| (!a[2] && !a[8] && !a[7] && !a[6] && !a[5] && !a[3] &&
a[1]));
assign en[0] = 1'b0;
assign en[1] = 1'b0;
assign en[2] = 1'b0;
assign en[3] = 1'b0;
assign en[4] = 1'b0;
assign en[5] = 1'b0;
assign en[6] = 1'b0;
assign en[7] = 1'b0;
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 KPR 74 KPR
3 KPR 75 KPR
4 KPR 76 KPR
5 KPR 77 KPR
6 KPR 78 KPR
7 KPR 79 KPR
8 VCC 80 KPR
9 KPR 81 KPR
10 KPR 82 KPR
11 KPR 83 KPR
12 KPR 84 VCC
13 KPR 85 KPR
14 KPR 86 KPR
15 KPR 87 KPR
16 KPR 88 KPR
17 KPR 89 GND
18 GND 90 GND
19 KPR 91 KPR
20 KPR 92 KPR
21 KPR 93 KPR
22 KPR 94 KPR
23 KPR 95 KPR
24 KPR 96 KPR
25 KPR 97 KPR
26 KPR 98 KPR
27 KPR 99 GND
28 KPR 100 KPR
29 GND 101 KPR
30 KPR 102 KPR
31 KPR 103 KPR
32 KPR 104 KPR
33 KPR 105 KPR
34 KPR 106 c<7>
35 KPR 107 c<6>
36 GND 108 GND
37 VCC 109 VCC
38 KPR 110 KPR
39 KPR 111 c<5>
40 KPR 112 KPR
41 KPR 113 c<4>
42 VCC 114 GND
43 KPR 115 c<3>
44 KPR 116 c<2>
45 KPR 117 KPR
46 KPR 118 c<1>
47 GND 119 c<0>
48 KPR 120 en<3>
49 KPR 121 KPR
50 KPR 122 TDO
51 KPR 123 GND
52 KPR 124 en<4>
53 KPR 125 en<5>
54 KPR 126 en<2>
55 VCC 127 VCC
56 a<8> 128 KPR
57 a<7> 129 KPR
58 a<6> 130 KPR
59 a<5> 131 en<1>
60 KPR 132 en<0>
61 a<4> 133 en<6>
62 GND 134 en<7>
63 TDI 135 KPR
64 a<3> 136 KPR
65 TMS 137 KPR
66 a<2> 138 KPR
67 TCK 139 KPR
68 KPR 140 KPR
69 a<1> 141 VCC
70 KPR 142 KPR
71 KPR 143 KPR
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ144
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
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