image.map.rpt

用于实现单片机功能的影音

+----------------------------------+-----------------+-----------------+-------------------------------------------------+
; image.vhd                        ; yes             ; User VHDL File  ; D:/study/实验室/image1280-50M/image.vhd         ;
; moving_object.vhd                ; yes             ; User VHDL File  ; D:/study/实验室/image1280-50M/moving_object.vhd ;
; moving.vhd                       ; yes             ; User VHDL File  ; D:/study/实验室/image1280-50M/moving.vhd        ;
; shinning.vhd                     ; yes             ; User VHDL File  ; D:/study/实验室/image1280-50M/shinning.vhd      ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+


+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                ;
+-----------------------------------+------------------------+
; Resource                          ; Usage                  ;
+-----------------------------------+------------------------+
; Total logic elements              ; 111                    ;
; Total combinational functions     ; 107                    ;
;     -- Total 4-input functions    ; 27                     ;
;     -- Total 3-input functions    ; 6                      ;
;     -- Total 2-input functions    ; 20                     ;
;     -- Total 1-input functions    ; 54                     ;
;     -- Total 0-input functions    ; 0                      ;
; Combinational cells for routing   ; 0                      ;
; Total registers                   ; 35                     ;
; Total logic cells in carry chains ; 70                     ;
; I/O pins                          ; 54                     ;
; Maximum fan-out node              ; moving_object:U1|color ;
; Maximum fan-out                   ; 48                     ;
; Total fan-out                     ; 422                    ;
; Average fan-out                   ; 2.56                   ;
+-----------------------------------+------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name     ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------+
; |image                     ; 111 (55)    ; 35           ; 0           ; 54   ; 0            ; 76 (29)      ; 4 (4)             ; 31 (22)          ; 70 (22)         ; |image                  ;
;    |moving_object:U1|      ; 56 (56)     ; 9            ; 0           ; 0    ; 0            ; 47 (47)      ; 0 (0)             ; 9 (9)            ; 48 (48)         ; |image|moving_object:U1 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 35    ;
; Number of registers using Synchronous Clear  ; 8     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 22    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 19    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/study/实验室/image1280-50M/image.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Nov 12 16:24:18 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cyclic -c image
Info: Found 2 design units, including 1 entities, in source file image.vhd
    Info: Found design unit 1: image-rtl
    Info: Found entity 1: image
Info: Found 2 design units, including 1 entities, in source file moving_object.vhd
    Info: Found design unit 1: moving_object-rtl
    Info: Found entity 1: moving_object
Info: Found 2 design units, including 1 entities, in source file moving.vhd
    Info: Found design unit 1: moving-rtl
    Info: Found entity 1: moving
Info: Found 2 design units, including 1 entities, in source file shinning.vhd
    Info: Found design unit 1: shinning-rtl
    Info: Found entity 1: shinning
Info: Elaborating entity "image" for the top level hierarchy
Info: Elaborating entity "moving_object" for hierarchy "moving_object:U1"
Info: Elaborating entity "moving" for hierarchy "moving:U2"
Info: Elaborating entity "shinning" for hierarchy "shinning:U3"
Warning: Reduced register "moving_object:U1|speed[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|speed[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|speed[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|speed[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|speed[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|speed[4]" with stuck data_in port to stuck value GND
Info: Power-up level of register "moving_object:U1|speed[3]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "moving_object:U1|speed[3]" with stuck data_in port to stuck value VCC
Warning: Reduced register "moving_object:U1|speed[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|speed[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|speed[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|speed[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|nn[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|nn[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "moving_object:U1|nn[0]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "pixs_out" stuck at VCC
Info: Implemented 165 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 53 output pins
    Info: Implemented 111 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
    Info: Processing ended: Mon Nov 12 16:24:21 2007
    Info: Elapsed time: 00:00:03