image.vhd

非常好的VHDL用于LCD显示的程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY image IS
PORT(   clk     : IN std_logic;
		clk_out : OUT std_logic;
		hs_out  : OUT std_logic;
		de_out  : BUFFER std_logic;
		vs_out  : OUT std_logic;
		pixs_out: OUT std_logic;
		out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		out_b_o   : OUT std_logic_vector(7 DOWNTO 0));

CONSTANT HAC:integer:=512;   -- horizontal active pixels 1448*1151
CONSTANT HFP:integer:=12;     -- horizontal front porch
CONSTANT HSY:integer:=68;     -- horizontal sync width (negative polarity)
CONSTANT HBP:integer:=80;     -- horizontal back porch
CONSTANT HTOT:integer:=672;
CONSTANT VAC:integer:=768;    -- vertical active pixels
CONSTANT VFP:integer:=3;    -- vertical front porch
CONSTANT VSY:integer:=6;      -- vertical sync width (negative polarity)
CONSTANT VBP:integer:=29;     -- vertical back porch
CONSTANT VTOT:integer:=806; -- vertical total lines (in 60 Hz field
END image;

ARCHITECTURE rtl OF image IS

SIGNAL hb : std_logic;
SIGNAL hs : std_logic;
SIGNAL vb : std_logic;
SIGNAL vs : std_logic;
SIGNAL clken_vcount : std_logic;--第几行的计数
SIGNAL clken_fcount : std_logic;--第几帧的计数
SIGNAL out1_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL pattern   :   std_logic_vector(4 DOWNTO 0);
SIGNAL vcountreg :   std_logic_vector(10 DOWNTO 0);
SIGNAL hcountreg :   std_logic_vector(10 DOWNTO 0);

COMPONENT moving_object IS PORT
		( clk    : IN std_logic;
		  vcount : IN std_logic_vector(10 DOWNTO 0);
		  hcount : IN std_logic_vector(10 DOWNTO 0);
		  clken_fcount: IN std_logic;
		  pattern   : IN std_logic_vector(4  DOWNTO 0);
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0))
;
END COMPONENT;

COMPONENT moving IS PORT
		( clk       : IN std_logic;
		  clken_fcount: IN std_logic;
		  de_out    : IN std_logic;
		  pattern   : IN std_logic_vector(4  DOWNTO 0);
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0))
		;
END COMPONENT;

COMPONENT shinning IS PORT
		( clk    : IN std_logic;
		  vcount : IN std_logic_vector(10 DOWNTO 0);
		  hcount : IN std_logic_vector(10 DOWNTO 0);
		  clken_fcount: IN std_logic;
		  pattern: IN std_logic_vector(4  DOWNTO 0);
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;

--产生行同步脉冲和行de
BEGIN
hcount: BLOCK 
SIGNAL hz : std_logic;
BEGIN
PROCESS (clk,hz)
BEGIN
IF (hz = '1') THEN
hcountreg <= (OTHERS =>'0');
ELSIF clk'event AND clk = '1' THEN
hcountreg <= hcountreg +1;
END IF;
END PROCESS;
hb <= '1' when hcountreg >=HBP+HSY AND hcountreg < HTOT-HFP
ELSE '0';
hs <='1' when hcountreg >=HSY AND hcountreg < HTOT
ELSE '0';
hz <= '1' when hcountreg = HTOT ELSE '0';
END BLOCK hcount;

--判断行脉冲上升延，产生列起始信号
vstart : BLOCK
SIGNAL inputa : std_logic;
SIGNAL inputb : std_logic;
BEGIN
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
inputb <= inputa;
inputa <= NOT hs;
END IF;
END PROCESS;
clken_vcount <= NOT inputb AND inputa;
END BLOCK vstart;

--产生列同步和de
vcount : BLOCK
SIGNAL vz : std_logic;
BEGIN
PROCESS (clk,vz)
BEGIN
IF(vz='1')THEN
vcountreg <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF clken_vcount = '1' THEN
vcountreg <= vcountreg +1;
END IF;
END IF;
END PROCESS;
vb <= '1' when vcountreg >=VBP+VSY AND vcountreg < VTOT-VFP
ELSE '0';
vs <='1' when vcountreg >=VSY AND vcountreg < VTOT
ELSE '0';
vz <= '1' when vcountreg = VTOT ELSE '0';
END BLOCK vcount;

--判断列脉冲上升延，产生帧起始信号
fstart : BLOCK
SIGNAL inputc : std_logic;
SIGNAL inputd : std_logic;
BEGIN
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
inputd <= inputc;
inputc <= NOT vs;
END IF;
END PROCESS;
clken_fcount <= NOT inputd AND inputc;
END BLOCK fstart;

U1 : moving_object
	PORT MAP
	(
		 clk  =>  clk,
		 vcount => vcountreg,
		 hcount => hcountreg,
		 clken_fcount => clken_fcount,
		 pattern => pattern,
		 out_r_e  => out1_r_e,
		 out_g_e  => out1_g_e,
		 out_b_e  => out1_b_e,
		 out_r_o  => out1_r_o,
		 out_g_o  => out1_g_o,
		 out_b_o  => out1_b_o
	);
	
U2 : moving
   PORT MAP
   (
		 clk    =>  clk,
		 de_out =>de_out,
		 clken_fcount => clken_fcount,
		 pattern => pattern,
		 out_r_e  => out2_r_e,
		 out_g_e  => out2_g_e,
		 out_b_e  => out2_b_e,
		 out_r_o  => out2_r_o,
		 out_g_o  => out2_g_o,
		 out_b_o  => out2_b_o
	);

U3: shinning
   PORT MAP
(
		 clk  =>  clk,
		 vcount => vcountreg,
		 hcount => hcountreg,
		 clken_fcount => clken_fcount,
		 pattern => pattern,
		 out_r_e  => out3_r_e,
		 out_g_e  => out3_g_e,
		 out_b_e  => out3_b_e,
		 out_r_o  => out3_r_o,
		 out_g_o  => out3_g_o,
		 out_b_o  => out3_b_o
		
	);

out_r_e <= out1_r_e;--can be chose 
out_g_e <= out1_g_e;
out_b_e <= out1_b_e;
out_r_o <= out1_r_o;--can be chose 
out_g_o <= out1_g_o;
out_b_o <= out1_b_o;

pattern <="00001";
pixs_out <='1'; 
de_out <=hb AND vb;
hs_out <=hs;
vs_out <=vs;
clk_out<=clk;
END rtl;