cpupack.vhd

Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin

library ieee ;
use ieee.std_logic_1164.all ;

package cpupack is

subtype nibble is std_logic_vector( 3 downto 0) ;
subtype byte is std_logic_vector( 7 downto 0) ;
subtype twelve is std_logic_vector( 11 downto 0) ;

constant zero_4 : nibble := "0000" ;
constant zero_8 : byte := "00000000" ;
constant zero_12 : twelve := "000000000000" ;

constant singleBI : std_logic_vector( 3 downto 0) := "1110" ;
constant cla : std_logic_vector( 3 downto 0) := "0001" ;
constant cma : std_logic_vector( 3 downto 0) := "0010" ;
constant cmc : std_logic_vector( 3 downto 0) := "0100" ;
constant stc : std_logic_vector( 3 downto 0) := "0101" ;
constant asl : std_logic_vector( 3 downto 0) := "1000" ;
constant asr : std_logic_vector( 3 downto 0) := "1001" ;
constant bra : std_logic_vector( 3 downto 0) := "1111" ;
constant jsr : std_logic_vector( 3 downto 0) := "1100" ;
constant orl : std_logic_vector( 3 downto 0) := "1101" ;
constant jmp : std_logic_vector( 2 downto 0) := "100" ;
constant sta : std_logic_vector( 2 downto 0) := "101" ;
constant lda : std_logic_vector( 2 downto 0) := "000" ;
constant anl : std_logic_vector( 2 downto 0) := "001" ;
constant adc : std_logic_vector( 2 downto 0) := "010" ;
constant sbb : std_logic_vector( 2 downto 0) := "011" ;

function set_if_zero ( x  : std_logic_vector ) return std_logic ;

end cpupack ;

package body cpupack is


function set_if_zero ( x  : std_logic_vector ) 
return std_logic is
variable zero : std_logic := '1' ;
begin
 FOR i in x'range loop
  if x(i) /= '0' then zero := '0' ; 
  exit ;
  end if ;
 end loop ;
 return zero ; 
end set_IF_ZERO ;

end cpupack ;