jh_cpu4.vhd

Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin

-- clock generation block 
-- single/double byte(s) instruction fetch
-- single byte instruction expanded
-- jsr instruction expand
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
use work.cpupack.all ;

entity jh_cpu4 is
  port( clk, intr : in  std_logic ;
        rd, wr    : out std_logic ;
        co, vo    : out std_logic ;
        pco   : inout TWELVE;
        databus : inout byte := "ZZZZZZZZ" ;
        adbus   : out TWELVE ) ;
end jh_cpu4 ;

architecture behavioral of jh_cpu4  is
   TYPE STATE_TYPE IS (s0, s1, s2, s3, S4, S5);
   SIGNAL state	: STATE_TYPE;
   signal clk1, clk2 : std_logic ;
   signal ring : std_logic_vector(7 downto 0) ;
   SIGNAL SBI, YES_JSR   : STD_LOGIC ;
   SIGNAL  IR1, IR2, TMP :BYTE ;
   SIGNAL  pc : TWELVE;

begin

----------------------------------------------------------------------------------------- 
---**************************************
clk_process :  --- clk1 and clk2 gereration block
   process(clk, intr) 
   variable q : std_logic_vector(7 downto 0) := "01100000";
   begin 
    If intr = '1' then 
       q := "01100000" ;
	elsIF (clk'EVENT AND clk= '1') THEN
         q := q(0) & q(7 downto 1)  ;            
		END IF;
     ---**************************************
    ring <= q ;
   end process ;
      
     clk1 <= ring(7) ;
     clk2 <= ring(3) ;
 ---**************************************
-----------------------------------------------------------------------------------------
  PROCESS (clk1, clk2)
   variable  ACC  : byte := ZERO_8;  
   variable  c, v : std_logic := '0' ;

    BEGIN
     ---**************************************
	IF (clk1'EVENT AND clk1 = '1') THEN

		  CASE state IS
            when s0=>
                               state <= s1 ;        
			WHEN s1=>
                            if intr='1' then
     	                      state <= s0;
                            elsif SBI ='1' THEN
                               state <= s3 ;
                            ELSE 
                               state <= s2 ;
                            end if ;
			WHEN s2 =>
                            if intr='1' then
			                   state <= s0;
                            elsif YES_JSR ='1' then
                               state <= s4 ;
                            end if ;
			WHEN s4=>
                            if intr='1' then
			                   state <= s0;
                            else
                               state <= s5;
                            end if ;
			WHEN s3 |S5=>
                            if intr='1' then
			                   state <= s0;
                            else
                               state <= s1 ;
                            end if ;
                  END CASE;
           --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
		IF state = s0 THEN
		   PC <= ZERO_12;
		ELSIF ((state =s1) or (state=s2) or (state =s5)) THEN
		   PC <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(PC)+1, 12) ;
		ELSIF  state = s4 THEN
		   PC <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(IR1(3 DOWNTO 0)&IR2)+1, 12) ;
		END IF;
			
           --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
		END IF;
     ---**************************************

----===============================================================
     IF (clk2'EVENT AND clk2 = '1') THEN
         --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
          IF STATE = S0 THEN 
                  ACC := "10101100" ; --ZERO_8 ;
             ELSIF STATE = S3 THEN    
                   case IR1(3 downto 0)is
                     when cla => 
                       acc := ZERO_8 ;
                     when cma => 
                       acc := NOT acc ;
                     when cmc => 
                       c := not c  ;
                     when stc =>
                       c:= '1' ;
                     when asl => 
                       if acc(7)/= acc(6) then V := '1' ; end if ;
                       c := acc(7)  ;
                       acc := acc(6 DOWNTO 0) & '0' ;
                     when asr => 
                       C := ACC(0) ; 
                       acc := ACC(7) & ACC(7 DOWNTO 1) ;
                     when others => NULL ;                   
                   end case ;       
             END IF ;  
        --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
			IF state = s0 THEN
				IR1 <= ZERO_8;
			ELSIF state = s1 THEN
				IR1 <= DATABUS ;
	         	END IF;
         --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
			IF state = s0 THEN
				IR2 <= ZERO_8;
				TMP <= ZERO_8;
			ELSIF (state = s2) THEN
				IR2 <= DATABUS ;
                TMP <= DATABUS ;
            ELSIF STATE = S4 THEN              
          		TMP  <= "0000" & pc(11 downto 8) ;
			END IF;
         --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
       END IF ;
----===============================================================            

    pco <= pc ;
    co <= c ;
    vo <= v ; 
END PROCESS;

    SBI <= '1' WHEN (IR1( 7 downto 4) = singleBI) ELSE
           '0'  ;
    YES_JSR <= '1' WHEN (IR1( 7 downto 4) = JSR) ELSE
           '0'  ;
    AD_BUS:
       WITH STATE SELECT
       	ADBUS <= "ZZZZZZZZZZZZ" WHEN s0 |s3,
       		   pc WHEN s1 |s2 |s5,        
                   IR1( 3 DOWNTO 0) & IR2 WHEN s4 ;
    DATA_BUS:
       WITH STATE SELECT
       	DATABUS <= pco( 7 DOWNTO 0)  WHEN s4,
                   TMP  WHEN s5,
                   "ZZZZZZZZ" WHEN OTHERS ;

    READ:
       WITH STATE SELECT
       	RD <= '1' WHEN s1 | S2,
              '0' WHEN OTHERS ;
    WRITE:
       WITH STATE SELECT
       	WR <= '1' WHEN s4| s5,
              '0' WHEN OTHERS ;
       	         
-----------------------------------------------------------------------------------------
end behavioral  ;