jh_cpu1.vhd

Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin

-- clock generation block 
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
use work.cpupack.all ;

entity jh_cpu1 is
  port( clk, intr : in  std_logic ;
        clk1,clk2   : out std_logic ) ;
end jh_cpu1 ;

architecture behavioral of jh_cpu1  is
signal ring : std_logic_vector(7 downto 0) ;
begin

----------------------------------------------------------------------------------------- 
 clk_process :  --- clk1 and clk2 gereration block
   process(clk, intr) 
   variable q : std_logic_vector(7 downto 0) := "01100000";
   begin 
   ---**************************************
    If intr = '1' then 
       q := "01100000" ;
	elsIF (clk'EVENT AND clk= '1') THEN
         q := q(0) & q(7 downto 1)  ;            
		END IF;
     ---**************************************
    ring <= q ;
   end process ;
      
     clk1 <= ring(7) ;
     clk2 <= ring(3) ;
-----------------------------------------------------------------------------------------
-- other VHDL codes     
-----------------------------------------------------------------------------------------
end behavioral  ;