📄 jh_cpu11.vhd
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-- clock generation block
-- single/double byte(s) instruction fetch
-- single byte instruction expanded
-- jsr instruction expanded
-- bra instruction expanded
-- Jmp instruction expanded
-- STA instruction expanded
-- LDA instruction expanded
-- ANL instruction expanded
-- ADC instruction expanded
-- SBB instruction expand
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
use work.cpupack.all ;
entity jh_cpu11 is
port( clk, intr : in std_logic ;
rd, wr : out std_logic ;
co, vo : inout std_logic ;
ZO, NO : inout std_logic ;
pco : inout TWELVE;
databus : inout byte := "ZZZZZZZZ" ;
adbus : out TWELVE ) ;
end jh_cpu11 ;
architecture behavioral of jh_cpu11 is
TYPE STATE_TYPE IS (s0, s1, s2, s3, S4, S5, S6, s7, s8, s9, s10, s11, s12, s13, s14, s15);
SIGNAL state : STATE_TYPE;
signal clk1, clk2 : std_logic ;
signal ring : std_logic_vector(7 downto 0) ;
SIGNAL SBI, YES_JSR, YES_BR : STD_LOGIC ;
SIGNAL IR1, IR2, TMP, ACCU :BYTE ;
SIGNAL pc, PCTMP : TWELVE;
begin
-----------------------------------------------------------------------------------------
---**************************************
clk_process : --- clk1 and clk2 gereration block
process(clk, intr)
variable q : std_logic_vector(7 downto 0) := "01100000";
begin
If intr = '1' then
q := "01100000" ;
elsIF (clk'EVENT AND clk= '1') THEN
q := q(0) & q(7 downto 1) ;
END IF;
---**************************************
ring <= q ;
end process ;
clk1 <= ring(7) ;
clk2 <= ring(3) ;
---**************************************
-----------------------------------------------------------------------------------------
PROCESS (clk1, clk2)
variable ACC : byte := ZERO_8;
variable acctmp : STD_LOGIC_VECTOR ( 8 DOWNTO 0) ;
variable c, v, n, z : std_logic := '0' ;
variable ext_acc, DTMP : integer range 0 to 511 ;
variable ext_c: integer range 0 to 1 ;
BEGIN
---**************************************
IF (clk1'EVENT AND clk1 = '1') THEN
CASE state IS
when s0=>
state <= s1 ;
WHEN s1=>
if intr='1' then
state <= s0;
elsif SBI ='1' THEN
state <= s3 ;
ELSE
state <= s2 ;
end if ;
WHEN s2 =>
if intr='1' then
state <= s0;
elsif YES_JSR ='1' then
state <= s4 ;
elsif (IR1( 7 downto 4) = BRA) THEN
IF YES_BR ='1' then
state <= s6 ;
ELSE
STATE <= S1 ;
END IF ;
elsif (IR1( 7 downto 5) = JMP) THEN
if IR1(4) ='1' then
state <= s7 ;
ELSE
STATE <= s10 ;
END IF ;
elsif IR1(4) ='1' then
state <= s7 ;
ELSIF (IR1( 7 downto 5) = STA) THEN
STATE <= s11 ;
elsif (IR1( 7 downto 5) = LDA) THEN
STATE <= S12 ;
elsif (IR1( 7 downto 5) = ANL) THEN
STATE <= S13 ;
elsif (IR1( 7 downto 5) = ADC ) THEN
STATE <= S14 ;
elsif (IR1( 7 downto 5) = SBB ) THEN
STATE <= S15 ;
end if ;
WHEN s4=>
if intr='1' then
state <= s0;
else
state <= s5;
end if ;
WHEN s7=>
if intr='1' then
state <= s0;
elsif (IR1( 7 downto 5) = JMP) THEN
state <= s8 ;
ELSIF (IR1( 7 downto 5) = STA) THEN
STATE <= s11 ;
elsif (IR1( 7 downto 5) = LDA) THEN
STATE <= S12 ;
elsif (IR1( 7 downto 5) = ANL) THEN
STATE <= S13 ;
elsif (IR1( 7 downto 5) = ADC ) THEN
STATE <= S14 ;
elsif (IR1( 7 downto 5) = SBB ) THEN
STATE <= S15 ;
end if ;
WHEN s8=>
if intr='1' then
state <= s0;
else
state <=s9 ;
end if ;
WHEN OTHERS =>
if intr='1' then
state <= s0;
else
state <= s1 ;
end if ;
END CASE;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
IF state = s0 THEN
PC <= ZERO_12;
ELSIF ((state =s1) or (state=s2) or (state =s5) ) THEN
PC <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(PC)+1, 12) ;
ELSIF STATE = S4 THEN
PC <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(IR1(3 DOWNTO 0)&IR2)+1, 12) ;
ELSIF (STATE = S6) THEN
PC(7 DOWNTO 0) <= IR2 ;
ELSIF ( (STATE =s9) OR (STATE =s10)) THEN
PC <= IR1( 3 DOWNTO 0) & IR2 ;
END IF;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
END IF;
---**************************************
----===============================================================
IF (clk2'EVENT AND clk2 = '1') THEN
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
IF STATE = S0 THEN
ACC := "10101100" ; --ZERO_8 ;
ELSIF STATE = S3 THEN
case IR1(3 downto 0)is
when cla =>
acc := ZERO_8 ;
when cma =>
acc := NOT acc ;
when cmc =>
c := not c ;
when stc =>
c:= '1' ;
when asl =>
if acc(7)/= acc(6) then V := '1' ; end if ;
c := acc(7) ;
acc := acc(6 DOWNTO 0) & '0' ;
when asr =>
C := ACC(0) ;
acc := ACC(7) & ACC(7 DOWNTO 1) ;
when others => NULL ;
end case ;
ELSIF STATE = s7 THEN
PCTMP <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(IR1(3 DOWNTO 0)& TMP)+1, 12) ;
ELSIF STATE = S12 THEN --LDA OPERATION
ACC := DATABUS ;
ELSIF STATE = S13 THEN -- ANL OPERATION
ACCTMP := acc and DATABUS ;
ACC := ACCTMP ;
ELSIF (STATE = S14) or (state = s15) THEN
--#### starting of adc/sbb opertion
if c='1' then
ext_c := 1 ;
else
ext_c := 0 ;
end if ;
DTMP := conv_integer(DATABUS) ;
ext_acc := conv_integer(acc) ;
if (state = s14) then
acctmp := CONV_STD_LOGIC_VECTOR(ext_acc+ DTMP + ext_c, 9) ;
else
acctmp := CONV_STD_LOGIC_VECTOR(ext_acc- DTMP - ext_c, 9) ;
end if ;
if (databus(databus'left) = acc(acc'left)) and (acctmp(acc'left)/= acc(acc'left)) then
v := '1' ; --- overflow
else
v := '0' ; --- underflow
end if ;
ACC := ACCTMP(7 downto 0) ;
c := acctmp(8) ;
END IF ;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
IF state = s0 THEN
IR1 <= ZERO_8;
ELSIF (state = s1) THEN
IR1 <= DATABUS ;
ELSIF (state =s9) THEN
IR1 <= TMP ;
END IF;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
IF state = s0 THEN
IR2 <= ZERO_8;
TMP <= ZERO_8;
ELSIF (state = s2) THEN
IR2 <= DATABUS ;
TMP <= DATABUS ;
ELSIF STATE = S4 THEN
TMP <= "0000" & pc(11 downto 8) ;
ELSIF (STATE = s7) THEN
IR2 <= DATABUS ;
ELSIF (STATE = s8) THEN
TMP <= DATABUS ;
END IF;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
END IF ;
----===============================================================
ACCU <= ACC ;
pco <= pc ;
co <= c ;
vo <= v ;
END PROCESS;
ZO <= '1' WHEN accu= zero_8 ELSE
'0' ;
NO <= ACCU(7) ;
SBI <= '1' WHEN (IR1( 7 downto 4) = singleBI) ELSE
'0' ;
YES_JSR <= '1' WHEN (IR1( 7 downto 4) = JSR) ELSE
'0' ;
YES_BR <= '1' WHEN ((IR1(3)= '1' AND VO='1')OR (IR1(2)= '1' AND Co='1')
OR(IR1(1)= '1' AND ZO='1')OR (IR1(0)= '1' AND NO='1')) ELSE
'0' ;
AD_BUS:
WITH STATE SELECT
ADBUS <= "ZZZZZZZZZZZZ" WHEN s0 |s3 |S6 | s10 |s9,
pc WHEN s1 |s2 | s5,
IR1(3 DOWNTO 0) & IR2 WHEN S4 | s11 |s12 |s13 | s14 | s15,
IR1(3 DOWNTO 0) & TMP WHEN s7,
PCTMP WHEN s8 ;
DATA_BUS:
WITH STATE SELECT
DATABUS <= pco( 7 DOWNTO 0) WHEN s4,
TMP when s5,
accu when s11,
"ZZZZZZZZ" WHEN OTHERS ;
READ:
WITH STATE SELECT
RD <= '1' WHEN s1 | S2 |s7 |s8 | s12 |s13 | s14 | s15,
'0' WHEN OTHERS ;
WRITE:
WITH STATE SELECT
WR <= '1' WHEN s4 | s5 | s11,
'0' WHEN OTHERS ;
-----------------------------------------------------------------------------------------
end behavioral ;
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