ex_319_tb_task.v

GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interfa

`timescale 1 ns/1 ns

module testbench;
reg		reset, clk;
reg	[7:0] 	addr;
reg		rd_n, wr_n;
wire	[7:0]	data, gpio0, gpio1, gpio2, gpio3, gpio4, gpio5;

reg	[7:0] 	data_out;
reg	[7:0]	gp0_i, gp1_i, gp2_i, gp3_i, gp4_i, gp5_i;
reg		data_ctl;
reg		p0_ctl, p1_ctl, p2_ctl, p3_ctl, p4_ctl, p5_ctl;

EX_319_tristatebus_gpio_top EX319_instance(
	.reset(reset), .clk(clk), .addr(addr),
	.rd_n(rd_n), .wr_n(wr_n), .data(data),
	.gpio0(gpio0), .gpio1(gpio1), .gpio2(gpio2),
	.gpio3(gpio3), .gpio4(gpio4), .gpio5(gpio5) );

assign data = (data_ctl==1'b1) ? data_out : 8'hz;

assign gpio0 = (p0_ctl==1'b1) ? gp0_i : 8'hz;
assign gpio1 = (p1_ctl==1'b1) ? gp1_i : 8'hz;
assign gpio2 = (p2_ctl==1'b1) ? gp2_i : 8'hz;
assign gpio3 = (p3_ctl==1'b1) ? gp3_i : 8'hz;
assign gpio4 = (p4_ctl==1'b1) ? gp4_i : 8'hz;
assign gpio5 = (p5_ctl==1'b1) ? gp5_i : 8'hz;

// set up clk with 20 ns period 50 MHz
parameter clkper = 20;
initial
begin
	clk = 1;	// Time = 0
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

task asyn_mem_write;
input	[7:0]	wr_addr, wr_data;
begin
 addr     = wr_addr;
 data_ctl = 1'b1;
 data_out = wr_data;
 #50;
 wr_n     = 1'b0;
 #200;
 wr_n     = 1'b1;
 #50;
 addr     = 8'h00;
 data_ctl = 1'b0;
 data_out = 8'h00;
 #100;
end
endtask

task asyn_mem_read;
input	[7:0]	rd_addr;
begin
 addr     = rd_addr;
 #50;
 rd_n     = 1'b0;
 #200;
 rd_n     = 1'b1;
 #50;
 addr     = 8'h00;
 #100;
end
endtask

initial
begin
 reset    = 1'b0;		// Time = 0
 addr     = 8'h00;
 rd_n     = 1'b1;
 wr_n     = 1'b1;
 data_ctl = 1'b0;
 p0_ctl   = 1'b0;
 p1_ctl   = 1'b1;		// config gpio1 as input port
 p2_ctl   = 1'b0;
 p3_ctl   = 1'b1;		// config gpio3 as input port
 p4_ctl   = 1'b0;
 p5_ctl   = 1'b1;		// config gpio5 as input port
 data_out = 8'h00;
 gp0_i    = 8'h00;
 gp1_i    = 8'h38;		// drive gpio1 0x38
 gp2_i    = 8'h00;
 gp3_i    = 8'h55;		// drive gpio3 0x55
 gp4_i    = 8'h00;
 gp5_i    = 8'h68;		// drive gpio5 0x68

 #105;				// Time = 105
 reset  = 1'b1;
 #100;
 asyn_mem_write(8'hF3,8'b0000_0101);
 asyn_mem_write(8'hF7,8'b0000_0010);
 asyn_mem_write(8'hF0,8'haa);
 asyn_mem_write(8'hF2,8'hbb);
 asyn_mem_write(8'hF5,8'hcc);

 asyn_mem_read(8'hF1);
 asyn_mem_read(8'hF4);
 asyn_mem_read(8'hF6);
end
endmodule