ex_319_top.v

GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interfa

// (1) 48 GPIO (General Purpose Input and Output ports)
//     control points with microprocessor programmable
//     tri-state bus interface.
// (2) bus interface :	1. addr : address bus
//			2. rd_n, wr_n : control bus
//			3. data : tri-state data bus
// (3) two submodules each of which supports
//     three-byte GPIO ports.
// (4) each GPIO port (8 control points) can be programmed
//     either as input ports or as output ports.
// (5) port addresses :
//	GPIO_U0 : F0~F3 (F0~F2 : GPIO registers,
//			 F3    : control register)
//	GPIO_U1 : F4~F7 (F4~F6 : GPIO registers,
//			 F7    : control register)
// (6) control registers F3 and F7:
//		bit 0 :	1 => config gpio0 as output ports
//			0 => config gpio0 as input ports
//		bit 1 : 1 => config gpio1 as output ports
//			0 => config gpio1 as input ports
//		bit 2 : 1 => config gpio2 as output ports
//			0 => config gpio2 as input ports

`timescale 1 ns/1 ns

module EX_319_tristatebus_gpio_top (
		reset, clk, addr, rd_n, wr_n, data,
		gpio0, gpio1, gpio2, gpio3, gpio4, gpio5 );
input		reset, clk;
input	[7:0]	addr;
input		rd_n, wr_n;
inout 	[7:0]	data, gpio0, gpio1, gpio2, gpio3, gpio4, gpio5;
wire	[7:0]	data, gpio0, gpio1, gpio2, gpio3, gpio4, gpio5;

reg	[7:0]	addr_reg;
reg		rd_n_reg, wr_n_reg;
wire		cs_n_0, cs_n_1;

assign cs_n_0 = (addr_reg[7:2]==6'b1111_00)? 1'b0 : 1'b1;
assign cs_n_1 = (addr_reg[7:2]==6'b1111_01)? 1'b0 : 1'b1;

// synchronization of address and control bus
always@(posedge clk or negedge reset)
begin
  if(!reset) begin
    addr_reg <= #1 8'h0;
    rd_n_reg <= #1 1'b1;
    wr_n_reg <= #1 1'b1;
  end
  else begin
    addr_reg <= #1 addr;
    rd_n_reg <= #1 rd_n;
    wr_n_reg <= #1 wr_n;
  end
end

EX_319_tristatebus_gpio GPIO_U0(
	.reset(reset), .clk(clk), .addr_reg(addr_reg[1:0]),
	.rd_n_reg(rd_n_reg), .wr_n_reg(wr_n_reg),
	.cs_n_reg(cs_n_0), .data(data),
	.gpio0(gpio0), .gpio1(gpio1), .gpio2(gpio2) );

EX_319_tristatebus_gpio GPIO_U1(
	.reset(reset), .clk(clk), .addr_reg(addr_reg[1:0]),
	.rd_n_reg(rd_n_reg), .wr_n_reg(wr_n_reg),
	.cs_n_reg(cs_n_1), .data(data),
	.gpio0(gpio3), .gpio1(gpio4), .gpio2(gpio5) );

endmodule