add_22.vhd

22位流水线加法器

library lpm;
use lpm.lpm_components.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity add_22 is
	generic(width: integer:=22;
			width1: integer:=7;
			width2: integer:=7;
			width3: integer:=8;
			one: integer:=1);
	port(x,y: in std_logic_vector(width-1 downto 0);
		 sum: out std_logic_vector(width-1 downto 0);
		 clk: in std_logic);
end add_22;

architecture behavior of add_22 is
	signal l1,l2,r1,q1,v1,s1: std_logic_vector(width1-1 downto 0);
	signal l3,l4,r2,q2,h2,u2,v2,s2: std_logic_vector(width2-1 downto 0);
	signal l5,l6,r3,q3,h3,u3,v3,g3,s3: std_logic_vector(width3-1 downto 0);
	signal s: std_logic_vector(width-1 downto 0);
	signal cr1,cq1,cr2,cq2,cr3,cq3: std_logic_vector(one-1 downto 0);
	
	begin
		process
		begin
			wait until clk='1';
			for k in width1-1 downto 0 loop
				l1(k)<=x(k);
				l2(k)<=y(k);
			end loop;
			
			for k in width2-1 downto 0 loop
				l3(k)<=x(k+width1);
				l4(k)<=y(k+width1);
			end loop;
			
			for k in width3-1 downto 0 loop
				l5(k)<=x(k+width1+width2);
				l6(k)<=y(k+width1+width2);
			end loop;
		end process;
	------------------ first stage of the adder ------------------------
		add_1:lpm_add_sub
				generic map(lpm_width=>width1,
							lpm_representation=>"unsigned",
							lpm_direction=>"add")
				port map(dataa=>l1,datab=>l2,
						 result=>r1,cout=>cr1(0));
		reg_1:lpm_ff
				generic map(lpm_width=>width1)
				port map(data=>r1,q=>q1,clock=>clk);
		reg_2:lpm_ff
				generic map(lpm_width=>one)
				port map(data=>cr1,q=>cq1,clock=>clk);
				
		add_2:lpm_add_sub
				generic map(lpm_width=>width2,
							lpm_representation=>"unsigned",
							lpm_direction=>"add")
				port map(dataa=>l3,datab=>l4,
						 result=>r2,cout=>cr2(0));
		reg_3:lpm_ff
				generic map(lpm_width=>width2)
				port map(data=>r2,q=>q2,clock=>clk);
		reg_4:lpm_ff
				generic map(lpm_width=>one)
				port map(data=>cr2,q=>cq2,clock=>clk);
				
		add_3:lpm_add_sub
				generic map(lpm_width=>width3,
							lpm_representation=>"unsigned",
							lpm_direction=>"add")
				port map(dataa=>l5,datab=>l6,result=>r3);
		reg_5:lpm_ff
				generic map(lpm_width=>width3)
				port map(data=>r3,q=>q3,clock=>clk);
		
	------------------ second stage of the adder -----------------------
		--add result from MSB and carry from LSB
		h2<=(others=>'0');
		h3<=(others=>'0');
		reg_21:lpm_ff
				generic map(lpm_width=>width1)
				port map(data=>q1,q=>v1,clock=>clk);
		add_4:lpm_add_sub
				generic map(lpm_width=>width2,
							lpm_representation=>"unsigned",
							lpm_direction=>"add")
				port map(cin=>cq1(0),dataa=>q2,
						 datab=>h2,result=>u2,cout=>cr3(0));
		reg_22:lpm_ff
				generic map(lpm_width=>width2)
				port map(data=>u2,q=>v2,clock=>clk);
		reg_23:lpm_ff
				generic map(lpm_width=>one)
				port map(data=>cr3,q=>cq3,clock=>clk);
		add_5:lpm_add_sub
				generic map(lpm_width=>width3,
							lpm_representation=>"unsigned",
							lpm_direction=>"add")
				port map(cin=>cq2(0),dataa=>q3,
						 datab=>h3,result=>u3);
		reg_24:lpm_ff
				generic map(lpm_width=>width3)
				port map(data=>u3,q=>v3,clock=>clk);
	------------------- third stage of the adder ------------------------
		reg_31:lpm_ff
				generic map(lpm_width=>width1)
				port map(data=>v1,q=>s1,clock=>clk);
		reg_32:lpm_ff
				generic map(lpm_width=>width2)
				port map(data=>v2,q=>s2,clock=>clk);
		add6:lpm_add_sub
				generic map(lpm_width=>width3,
							lpm_representation=>"unsigned",
							lpm_direction=>"add")
				port map(cin=>cq3(0),dataa=>v3,
						 datab=>h3,result=>g3);
		reg_33:lpm_ff
				generic map(lpm_width=>width3)
				port map(data=>g3,q=>s3,clock=>clk);		
		process
		begin
			wait until clk='1';
			for k in width1-1 downto 0 loop
				s(k)<=s1(k);
			end loop;
			for k in width2-1 downto 0 loop
				s(k+width1)<=s2(k);
			end loop;
			for k in width3-1 downto 0 loop
				s(k+width1+width2)<=s3(k);
			end loop;
		end process;
		sum<=s;
end behavior;