📄 cdu6.rpt
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Device-Specific Information: c:\aclock2\cdu6.rpt
cdu6
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - F 02 AND2 0 3 0 1 |LPM_ADD_SUB:81|addcore:adder|:59
- 6 - F 02 OR2 0 3 0 1 |LPM_ADD_SUB:81|addcore:adder|:68
- 2 - F 02 DFFE + 1 1 1 0 :4
- 3 - F 02 DFFE + 1 2 1 1 SCOUNT63 (:10)
- 1 - F 02 DFFE + 1 2 1 3 SCOUNT62 (:11)
- 5 - F 02 DFFE + 1 2 1 3 SCOUNT61 (:12)
- 7 - F 02 DFFE + 1 0 1 4 SCOUNT60 (:13)
- 4 - F 02 OR2 ! 0 4 0 4 :54
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\aclock2\cdu6.rpt
cdu6
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 2/ 96( 2%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\aclock2\cdu6.rpt
cdu6
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 CLK
Device-Specific Information: c:\aclock2\cdu6.rpt
cdu6
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 CLR
Device-Specific Information: c:\aclock2\cdu6.rpt
cdu6
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
EN : INPUT;
-- Node name is 'CN'
-- Equation name is 'CN', type is output
CN = _LC2_F2;
-- Node name is 'COUNT60'
-- Equation name is 'COUNT60', type is output
COUNT60 = SCOUNT60;
-- Node name is 'COUNT61'
-- Equation name is 'COUNT61', type is output
COUNT61 = SCOUNT61;
-- Node name is 'COUNT62'
-- Equation name is 'COUNT62', type is output
COUNT62 = SCOUNT62;
-- Node name is 'COUNT63'
-- Equation name is 'COUNT63', type is output
COUNT63 = SCOUNT63;
-- Node name is ':13' = 'SCOUNT60'
-- Equation name is 'SCOUNT60', location is LC7_F2, type is buried.
SCOUNT60 = DFFE( _EQ001, GLOBAL( CLK), GLOBAL(!CLR), VCC, VCC);
_EQ001 = !EN & SCOUNT60
# EN & !SCOUNT60;
-- Node name is ':12' = 'SCOUNT61'
-- Equation name is 'SCOUNT61', location is LC5_F2, type is buried.
SCOUNT61 = DFFE( _EQ002, GLOBAL( CLK), GLOBAL(!CLR), VCC, VCC);
_EQ002 = !_LC4_F2 & !SCOUNT60 & SCOUNT61
# EN & !_LC4_F2 & SCOUNT60 & !SCOUNT61
# !EN & SCOUNT61;
-- Node name is ':11' = 'SCOUNT62'
-- Equation name is 'SCOUNT62', location is LC1_F2, type is buried.
SCOUNT62 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL(!CLR), VCC, VCC);
_EQ003 = EN & !_LC4_F2 & _LC6_F2
# !EN & SCOUNT62;
-- Node name is ':10' = 'SCOUNT63'
-- Equation name is 'SCOUNT63', location is LC3_F2, type is buried.
SCOUNT63 = DFFE( _EQ004, GLOBAL( CLK), GLOBAL(!CLR), VCC, VCC);
_EQ004 = !_LC4_F2 & !_LC8_F2 & SCOUNT63
# EN & !_LC4_F2 & _LC8_F2 & !SCOUNT63
# !EN & SCOUNT63;
-- Node name is '|LPM_ADD_SUB:81|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_F2', type is buried
_LC8_F2 = LCELL( _EQ005);
_EQ005 = SCOUNT60 & SCOUNT61 & SCOUNT62;
-- Node name is '|LPM_ADD_SUB:81|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_F2', type is buried
_LC6_F2 = LCELL( _EQ006);
_EQ006 = !SCOUNT61 & SCOUNT62
# !SCOUNT60 & SCOUNT62
# SCOUNT60 & SCOUNT61 & !SCOUNT62;
-- Node name is ':4'
-- Equation name is '_LC2_F2', type is buried
_LC2_F2 = DFFE( _EQ007, GLOBAL( CLK), GLOBAL(!CLR), VCC, VCC);
_EQ007 = EN & _LC4_F2
# !EN & _LC2_F2;
-- Node name is ':54'
-- Equation name is '_LC4_F2', type is buried
!_LC4_F2 = _LC4_F2~NOT;
_LC4_F2~NOT = LCELL( _EQ008);
_EQ008 = !SCOUNT62
# SCOUNT61
# SCOUNT63
# !SCOUNT60;
Project Information c:\aclock2\cdu6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,277K
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