cdu6.vhd

来自「数字秒表具有正及时倒计时功能包括一些设计要求和原资料」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CDU6 IS    
PORT(  CLK,CLR,EN: IN STD_LOGIC;           
               CN: OUT STD_LOGIC;
           COUNT6: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CDU6;
ARCHITECTURE ART OF CDU6 IS
SIGNAL SCOUNT6:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN 
COUNT6<=SCOUNT6;
PROCESS(CLK,CLR,EN)
  BEGIN 
    IF(CLR='1')THEN
       SCOUNT6<="0000";CN<='0';
ELSIF RISING_EDGE(CLK)THEN
        IF(EN='1')THEN
IF SCOUNT6="0101"THEN
SCOUNT6<="0000";CN<='1';
ELSE
SCOUNT6<=SCOUNT6+'1';CN<='0';
END IF;
END IF;
END IF;
END PROCESS;
END ART;