📄 mulx.rpt
字号:
Project Information c:\trangeaclock2\mulx.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/28/2008 00:06:17
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MULX
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
mulx EPF10K20TC144-4 35 7 0 0 0 % 58 5 %
User Pins: 35 7 0
Project Information c:\trangeaclock2\mulx.rpt
** FILE HIERARCHY **
|lpm_add_sub:114|
|lpm_add_sub:114|addcore:adder|
|lpm_add_sub:114|altshift:result_ext_latency_ffs|
|lpm_add_sub:114|altshift:carry_ext_latency_ffs|
|lpm_add_sub:114|altshift:oflow_ext_latency_ffs|
Device-Specific Information: c:\trangeaclock2\mulx.rpt
mulx
***** Logic for device 'mulx' compiled without errors.
Device: EPF10K20TC144-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R M M R
E E E E E E E E E E E E E E S E _ _ S S E
S S S S S S S S S S S S S S G S _ V S 1 S S 1 _ _ S S S
E E E E E G E E E E V E E E E G E N _ H 1 C E 0 H S _ _ 0 V 1 1 S _ _ E
R R R R R N R R R R C R R R R N R D 1 O 0 C R M O _ 1 1 M C 0 0 _ 1 1 R
V V V V V D V V V V C V V V V D V I M U M I V I U 1 0 M I C M M 1 M 0 V
E E E E E I E E E E I E E E E I E N S R S N E N R S S S N I S S S S S E
D D D D D O D D D D O D D D D O D T 0 0 0 T D 1 1 0 0 2 0 O 3 2 3 1 2 D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | SEG0
RESERVED | 8 101 | SEG1
RESERVED | 9 100 | OUTBCD1
RESERVED | 10 99 | RESERVED
M_10MIN3 | 11 98 | SEG2
S_10MS1 | 12 97 | RESERVED
S_100MS3 | 13 96 | RESERVED
M_1MIN2 | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | OUTBCD0
RESERVED | 18 91 | M_1MIN0
RESERVED | 19 EPF10K20TC144-4 90 | M_1MIN3
RESERVED | 20 89 | S_1S2
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | RESERVED
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | OUTBCD3
RESERVED | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | HOUR3
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R G R V V C C E G G M H V S S S M G S S O S V S
E E E N E E E E C E E E E N E C C L L N N N _ O C _ _ _ _ N _ _ U _ C _
S S S D S S S S C S S S S D S C C R K D D 1 U C 1 1 1 1 D 1 1 T 1 C 1
E E E I E E E E I E E E E I E I I I I M R I S M 0 0 I 0 0 B 0 I 0
R R R O R R R R O R R R R O R N N N N I 2 O 1 S S M O S 0 C 0 O 0
V V V V V V V V V V V V T T T T N 3 3 I 1 M D M M
E E E E E E E E E E E E 1 N S 2 S S
D D D D D D D D D D D D 2 0 2 1
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\trangeaclock2\mulx.rpt
mulx
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C1 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 17/22( 77%)
C3 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/22( 77%)
C5 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/22( 77%)
C6 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
C7 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 17/22( 77%)
C8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 13/22( 59%)
C9 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 1/22( 4%)
C11 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 36/96 ( 37%)
Total logic cells used: 58/1152 ( 5%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.41/4 ( 85%)
Total fan-in: 198/4608 ( 4%)
Total input pins required: 35
Total input I/O cell registers required: 0
Total output pins required: 7
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 58
Total flipflops required: 11
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/1152 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 8 0 8 0 8 2 8 8 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 0 8 0 8 2 8 8 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58/0
Device-Specific Information: c:\trangeaclock2\mulx.rpt
mulx
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 CLK
54 - - - -- INPUT G 0 0 0 0 CLR
56 - - - -- INPUT 0 0 0 4 EN
125 - - - -- INPUT 0 0 0 1 HOUR0
120 - - - 08 INPUT 0 0 0 1 HOUR1
60 - - - 12 INPUT 0 0 0 1 HOUR2
73 - - - 01 INPUT 0 0 0 1 HOUR3
91 - - C -- INPUT 0 0 0 1 M_1MIN0
59 - - - 12 INPUT 0 0 0 1 M_1MIN1
14 - - C -- INPUT 0 0 0 1 M_1MIN2
90 - - C -- INPUT 0 0 0 1 M_1MIN3
116 - - - 04 INPUT 0 0 0 1 M_10MIN0
121 - - - 10 INPUT 0 0 0 1 M_10MIN1
65 - - - 09 INPUT 0 0 0 1 M_10MIN2
11 - - C -- INPUT 0 0 0 1 M_10MIN3
126 - - - -- INPUT 0 0 0 2 S_1MS0
111 - - - 01 INPUT 0 0 0 2 S_1MS1
117 - - - 05 INPUT 0 0 0 2 S_1MS2
63 - - - 10 INPUT 0 0 0 2 S_1MS3
119 - - - 07 INPUT 0 0 0 1 S_1S0
62 - - - 11 INPUT 0 0 0 1 S_1S1
89 - - C -- INPUT 0 0 0 1 S_1S2
112 - - - 02 INPUT 0 0 0 1 S_1S3
124 - - - -- INPUT 0 0 0 2 S_10MS0
12 - - C -- INPUT 0 0 0 2 S_10MS1
113 - - - 03 INPUT 0 0 0 2 S_10MS2
114 - - - 04 INPUT 0 0 0 2 S_10MS3
118 - - - 06 INPUT 0 0 0 1 S_10S0
67 - - - 08 INPUT 0 0 0 1 S_10S1
110 - - - 01 INPUT 0 0 0 1 S_10S2
64 - - - 09 INPUT 0 0 0 1 S_10S3
68 - - - 07 INPUT 0 0 0 1 S_100MS0
72 - - - 03 INPUT 0 0 0 1 S_100MS1
70 - - - 05 INPUT 0 0 0 1 S_100MS2
13 - - C -- INPUT 0 0 0 1 S_100MS3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\trangeaclock2\mulx.rpt
mulx
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
92 - - C -- OUTPUT 0 1 0 0 OUTBCD0
100 - - A -- OUTPUT 0 1 0 0 OUTBCD1
69 - - - 06 OUTPUT 0 1 0 0 OUTBCD2
83 - - E -- OUTPUT 0 1 0 0 OUTBCD3
102 - - A -- OUTPUT 0 1 0 0 SEG0
101 - - A -- OUTPUT 0 1 0 0 SEG1
98 - - B -- OUTPUT 0 1 0 0 SEG2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\trangeaclock2\mulx.rpt
mulx
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 09 AND2 0 2 0 11 |LPM_ADD_SUB:114|addcore:adder|:55
- 1 - C 09 OR2 0 3 0 1 |LPM_ADD_SUB:114|addcore:adder|:69
- 6 - C 07 DFFE + 1 2 1 0 :36
- 2 - C 05 DFFE + 1 2 1 0 :38
- 6 - C 03 DFFE + 1 2 1 0 :40
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -