cdu10.vhd

数字秒表具有正及时倒计时功能包括一些设计要求和原资料

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CDU10 IS    
PORT(  CLK:    IN STD_LOGIC;
       CLR:    IN STD_LOGIC;
       EN:     IN STD_LOGIC;
       CN:     OUT STD_LOGIC;
       COUNT10:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CDU10;
ARCHITECTURE ART OF CDU10 IS
SIGNAL SCOUNT10:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN 
COUNT10<=SCOUNT10;
PROCESS(CLK,CLR,EN)
  BEGIN 
    IF(CLR='1')THEN
       SCOUNT10<="0000";CN<='0';
ELSIF RISING_EDGE(CLK)THEN
        IF(EN='1')THEN
IF SCOUNT10="1001"THEN
        CN<='1';
SCOUNT10<="0000";
ELSE
   CN<='0';
   SCOUNT10<=SCOUNT10+'1';
END IF;
END IF;
END IF;
END PROCESS;
END ART;