📄 count.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\trangeaclock2\count.rpt
count
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - D -- OUTPUT 0 1 0 0 HOUR0
23 - - D -- OUTPUT 0 1 0 0 HOUR1
22 - - D -- OUTPUT 0 1 0 0 HOUR2
88 - - D -- OUTPUT 0 1 0 0 HOUR3
30 - - F -- OUTPUT 0 1 0 0 M_1MIN0
78 - - F -- OUTPUT 0 1 0 0 M_1MIN1
36 - - - 24 OUTPUT 0 1 0 0 M_1MIN2
33 - - F -- OUTPUT 0 1 0 0 M_1MIN3
18 - - D -- OUTPUT 0 1 0 0 M_10MIN0
20 - - D -- OUTPUT 0 1 0 0 M_10MIN1
17 - - D -- OUTPUT 0 1 0 0 M_10MIN2
21 - - D -- OUTPUT 0 1 0 0 M_10MIN3
92 - - C -- OUTPUT 0 1 0 0 S_1MS0
116 - - - 04 OUTPUT 0 1 0 0 S_1MS1
89 - - C -- OUTPUT 0 1 0 0 S_1MS2
91 - - C -- OUTPUT 0 1 0 0 S_1MS3
109 - - A -- OUTPUT 0 1 0 0 S_1S0
102 - - A -- OUTPUT 0 1 0 0 S_1S1
7 - - A -- OUTPUT 0 1 0 0 S_1S2
8 - - A -- OUTPUT 0 1 0 0 S_1S3
13 - - C -- OUTPUT 0 1 0 0 S_10MS0
11 - - C -- OUTPUT 0 1 0 0 S_10MS1
14 - - C -- OUTPUT 0 1 0 0 S_10MS2
90 - - C -- OUTPUT 0 1 0 0 S_10MS3
32 - - F -- OUTPUT 0 1 0 0 S_10S0
31 - - F -- OUTPUT 0 1 0 0 S_10S1
81 - - F -- OUTPUT 0 1 0 0 S_10S2
80 - - F -- OUTPUT 0 1 0 0 S_10S3
100 - - A -- OUTPUT 0 1 0 0 S_100MS0
101 - - A -- OUTPUT 0 1 0 0 S_100MS1
143 - - A -- OUTPUT 0 1 0 0 S_100MS2
144 - - A -- OUTPUT 0 1 0 0 S_100MS3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\trangeaclock2\count.rpt
count
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - F 19 AND2 0 3 0 1 |CDU6:U5|LPM_ADD_SUB:81|addcore:adder|:59
- 6 - F 19 OR2 0 3 0 1 |CDU6:U5|LPM_ADD_SUB:81|addcore:adder|:68
- 3 - F 24 DFFE 1 2 0 5 |CDU6:U5|:4
- 2 - F 19 DFFE 1 3 1 1 |CDU6:U5|SCOUNT63 (|CDU6:U5|:10)
- 1 - F 19 DFFE 1 3 1 3 |CDU6:U5|SCOUNT62 (|CDU6:U5|:11)
- 3 - F 19 DFFE 1 3 1 3 |CDU6:U5|SCOUNT61 (|CDU6:U5|:12)
- 5 - F 19 DFFE 1 1 1 4 |CDU6:U5|SCOUNT60 (|CDU6:U5|:13)
- 8 - F 19 AND2 0 4 0 4 |CDU6:U5|:54
- 7 - D 17 AND2 0 3 0 1 |CDU6:U7|LPM_ADD_SUB:81|addcore:adder|:59
- 6 - D 17 OR2 0 3 0 1 |CDU6:U7|LPM_ADD_SUB:81|addcore:adder|:68
- 1 - D 18 DFFE 1 2 0 4 |CDU6:U7|:4
- 5 - D 17 DFFE 1 3 1 1 |CDU6:U7|SCOUNT63 (|CDU6:U7|:10)
- 1 - D 17 DFFE 1 3 1 3 |CDU6:U7|SCOUNT62 (|CDU6:U7|:11)
- 4 - D 17 DFFE 1 3 1 3 |CDU6:U7|SCOUNT61 (|CDU6:U7|:12)
- 2 - D 17 DFFE 1 1 1 4 |CDU6:U7|SCOUNT60 (|CDU6:U7|:13)
- 8 - D 17 AND2 0 4 0 4 |CDU6:U7|:54
- 5 - C 04 AND2 0 3 0 1 |CDU10:UL|LPM_ADD_SUB:82|addcore:adder|:59
- 2 - C 04 OR2 0 3 0 1 |CDU10:UL|LPM_ADD_SUB:82|addcore:adder|:68
- 8 - C 16 DFFE + 1 1 0 5 |CDU10:UL|:4
- 8 - C 04 DFFE + 1 2 1 1 |CDU10:UL|SCOUNT103 (|CDU10:UL|:10)
- 7 - C 04 DFFE + 1 2 1 3 |CDU10:UL|SCOUNT102 (|CDU10:UL|:11)
- 1 - C 04 DFFE + 1 2 1 3 |CDU10:UL|SCOUNT101 (|CDU10:UL|:12)
- 4 - C 04 DFFE + 1 0 1 4 |CDU10:UL|SCOUNT100 (|CDU10:UL|:13)
- 3 - C 04 AND2 0 4 0 4 |CDU10:UL|:54
- 7 - C 16 AND2 0 3 0 1 |CDU10:U2|LPM_ADD_SUB:82|addcore:adder|:59
- 4 - C 16 OR2 0 3 0 1 |CDU10:U2|LPM_ADD_SUB:82|addcore:adder|:68
- 3 - A 13 DFFE 1 2 0 5 |CDU10:U2|:4
- 6 - C 16 DFFE 1 3 1 1 |CDU10:U2|SCOUNT103 (|CDU10:U2|:10)
- 5 - C 16 DFFE 1 3 1 3 |CDU10:U2|SCOUNT102 (|CDU10:U2|:11)
- 1 - C 16 DFFE 1 3 1 3 |CDU10:U2|SCOUNT101 (|CDU10:U2|:12)
- 2 - C 16 DFFE 1 1 1 4 |CDU10:U2|SCOUNT100 (|CDU10:U2|:13)
- 3 - C 16 AND2 0 4 0 4 |CDU10:U2|:54
- 8 - A 13 AND2 0 3 0 1 |CDU10:U3|LPM_ADD_SUB:82|addcore:adder|:59
- 5 - A 13 OR2 0 3 0 1 |CDU10:U3|LPM_ADD_SUB:82|addcore:adder|:68
- 2 - A 23 DFFE 1 2 0 5 |CDU10:U3|:4
- 2 - A 13 DFFE 1 3 1 1 |CDU10:U3|SCOUNT103 (|CDU10:U3|:10)
- 1 - A 13 DFFE 1 3 1 3 |CDU10:U3|SCOUNT102 (|CDU10:U3|:11)
- 4 - A 13 DFFE 1 3 1 3 |CDU10:U3|SCOUNT101 (|CDU10:U3|:12)
- 6 - A 13 DFFE 1 1 1 4 |CDU10:U3|SCOUNT100 (|CDU10:U3|:13)
- 7 - A 13 AND2 0 4 0 4 |CDU10:U3|:54
- 6 - A 23 AND2 0 3 0 1 |CDU10:U4|LPM_ADD_SUB:82|addcore:adder|:59
- 4 - A 23 OR2 0 3 0 1 |CDU10:U4|LPM_ADD_SUB:82|addcore:adder|:68
- 4 - F 19 DFFE 1 2 0 5 |CDU10:U4|:4
- 8 - A 23 DFFE 1 3 1 1 |CDU10:U4|SCOUNT103 (|CDU10:U4|:10)
- 7 - A 23 DFFE 1 3 1 3 |CDU10:U4|SCOUNT102 (|CDU10:U4|:11)
- 3 - A 23 DFFE 1 3 1 3 |CDU10:U4|SCOUNT101 (|CDU10:U4|:12)
- 1 - A 23 DFFE 1 1 1 4 |CDU10:U4|SCOUNT100 (|CDU10:U4|:13)
- 5 - A 23 AND2 0 4 0 4 |CDU10:U4|:54
- 8 - F 24 AND2 0 3 0 1 |CDU10:U6|LPM_ADD_SUB:82|addcore:adder|:59
- 7 - F 24 OR2 0 3 0 1 |CDU10:U6|LPM_ADD_SUB:82|addcore:adder|:68
- 3 - D 17 DFFE 1 2 0 5 |CDU10:U6|:4
- 5 - F 24 DFFE 1 3 1 1 |CDU10:U6|SCOUNT103 (|CDU10:U6|:10)
- 4 - F 24 DFFE 1 3 1 3 |CDU10:U6|SCOUNT102 (|CDU10:U6|:11)
- 6 - F 24 DFFE 1 3 1 3 |CDU10:U6|SCOUNT101 (|CDU10:U6|:12)
- 2 - F 24 DFFE 1 1 1 4 |CDU10:U6|SCOUNT100 (|CDU10:U6|:13)
- 1 - F 24 AND2 0 4 0 4 |CDU10:U6|:54
- 8 - D 18 AND2 0 3 0 1 |CDU10:U8|LPM_ADD_SUB:82|addcore:adder|:59
- 5 - D 18 OR2 0 3 0 1 |CDU10:U8|LPM_ADD_SUB:82|addcore:adder|:68
- 4 - D 18 DFFE 1 3 1 1 |CDU10:U8|SCOUNT103 (|CDU10:U8|:10)
- 6 - D 18 DFFE 1 3 1 3 |CDU10:U8|SCOUNT102 (|CDU10:U8|:11)
- 7 - D 18 DFFE 1 3 1 3 |CDU10:U8|SCOUNT101 (|CDU10:U8|:12)
- 3 - D 18 DFFE 1 1 1 4 |CDU10:U8|SCOUNT100 (|CDU10:U8|:13)
- 2 - D 18 OR2 ! 0 4 0 3 |CDU10:U8|:54
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\trangeaclock2\count.rpt
count
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 3/ 96( 3%) 2/ 48( 4%) 3/ 48( 6%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
D: 4/ 96( 4%) 0/ 48( 0%) 8/ 48( 16%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 4/ 96( 4%) 0/ 48( 0%) 7/ 48( 14%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\trangeaclock2\count.rpt
count
** CLOCK SIGNALS **
Type Fan-out Name
DFF 6 |CDU6:U5|:4
DFF 6 |CDU10:UL|:4
DFF 6 |CDU10:U2|:4
DFF 6 |CDU10:U3|:4
DFF 6 |CDU10:U4|:4
DFF 6 |CDU10:U6|:4
DFF 5 |CDU6:U7|:4
INPUT 5 CLK
Device-Specific Information: c:\trangeaclock2\count.rpt
count
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 39 CLR
Device-Specific Information: c:\trangeaclock2\count.rpt
count
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
EN : INPUT;
-- Node name is 'HOUR0'
-- Equation name is 'HOUR0', type is output
HOUR0 = _LC3_D18;
-- Node name is 'HOUR1'
-- Equation name is 'HOUR1', type is output
HOUR1 = _LC7_D18;
-- Node name is 'HOUR2'
-- Equation name is 'HOUR2', type is output
HOUR2 = _LC6_D18;
-- Node name is 'HOUR3'
-- Equation name is 'HOUR3', type is output
HOUR3 = _LC4_D18;
-- Node name is 'M_1MIN0'
-- Equation name is 'M_1MIN0', type is output
M_1MIN0 = _LC2_F24;
-- Node name is 'M_1MIN1'
-- Equation name is 'M_1MIN1', type is output
M_1MIN1 = _LC6_F24;
-- Node name is 'M_1MIN2'
-- Equation name is 'M_1MIN2', type is output
M_1MIN2 = _LC4_F24;
-- Node name is 'M_1MIN3'
-- Equation name is 'M_1MIN3', type is output
M_1MIN3 = _LC5_F24;
-- Node name is 'M_10MIN0'
-- Equation name is 'M_10MIN0', type is output
M_10MIN0 = _LC2_D17;
-- Node name is 'M_10MIN1'
-- Equation name is 'M_10MIN1', type is output
M_10MIN1 = _LC4_D17;
-- Node name is 'M_10MIN2'
-- Equation name is 'M_10MIN2', type is output
M_10MIN2 = _LC1_D17;
-- Node name is 'M_10MIN3'
-- Equation name is 'M_10MIN3', type is output
M_10MIN3 = _LC5_D17;
-- Node name is 'S_1MS0'
-- Equation name is 'S_1MS0', type is output
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