📄 dled.rpt
字号:
42 - - - -- INPUT 0 0 0 22 start
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\2\dled.rpt
dled
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
37 - - - 09 OUTPUT 0 1 0 0 LED_A
28 - - C -- OUTPUT 0 1 0 0 LED_B
59 - - C -- OUTPUT 0 1 0 0 LED_C
61 - - C -- OUTPUT 0 1 0 0 LED_D
48 - - - 15 OUTPUT 0 0 0 0 LED_DP
29 - - C -- OUTPUT 0 1 0 0 LED_E
27 - - C -- OUTPUT 0 1 0 0 LED_F
58 - - C -- OUTPUT 0 1 0 0 LED_G
51 - - - 18 OUTPUT 0 1 0 0 LED_SA
60 - - C -- OUTPUT 0 1 0 0 LED_SB
62 - - C -- OUTPUT 0 1 0 0 LED_SC
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\2\dled.rpt
dled
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 13 OR2 0 2 0 1 |c6:MH3|LPM_ADD_SUB:145|addcore:adder|pcarry1
- 5 - C 14 DFFE + 1 2 0 5 |c6:MH3|temp2 (|c6:MH3|:11)
- 2 - C 14 DFFE + 1 2 0 5 |c6:MH3|temp1 (|c6:MH3|:12)
- 1 - C 14 DFFE + 1 2 0 5 |c6:MH3|temp0 (|c6:MH3|:13)
- 7 - C 14 OR2 0 4 0 1 |c6:MH3|:195
- 8 - C 14 OR2 0 4 0 1 |c6:MH3|:196
- 4 - C 14 OR2 0 4 0 1 |c6:MH3|:200
- 3 - C 14 OR2 0 4 0 1 |c6:MH3|:204
- 6 - C 14 AND2 0 2 0 1 |c6:MH3|:205
- 5 - C 02 OR2 0 2 0 1 |c6:SH2|LPM_ADD_SUB:85|addcore:adder|:59
- 5 - C 08 DFFE + 1 2 0 8 |c6:SH2|temp2 (|c6:SH2|:11)
- 6 - C 02 DFFE + 1 1 0 8 |c6:SH2|temp1 (|c6:SH2|:12)
- 8 - C 02 DFFE + 1 2 0 8 |c6:SH2|temp0 (|c6:SH2|:13)
- 4 - C 02 OR2 ! 0 3 0 1 |c6:SH2|:66
- 3 - C 08 OR2 0 3 0 1 |c6:SH2|:161
- 2 - C 08 OR2 0 4 0 1 |c6:SH2|:195
- 4 - C 08 OR2 0 4 0 1 |c6:SH2|:196
- 2 - C 02 OR2 0 4 0 1 |c6:SH2|:200
- 7 - C 02 OR2 0 4 0 1 |c6:SH2|:203
- 3 - C 02 OR2 ! 0 4 0 6 |c6:SH2|:265
- 1 - C 02 OR2 ! 0 4 0 6 |c6:SH2|:289
- 6 - C 18 AND2 0 2 0 1 |c10:ML3|LPM_ADD_SUB:102|addcore:adder|:55
- 3 - C 15 OR2 0 2 0 1 |c10:ML3|LPM_ADD_SUB:102|addcore:adder|:67
- 4 - C 18 OR2 0 3 0 1 |c10:ML3|LPM_ADD_SUB:179|addcore:adder|pcarry2
- 1 - C 18 DFFE + 1 2 0 5 |c10:ML3|temp3 (|c10:ML3|:12)
- 2 - C 16 DFFE + 1 2 0 8 |c10:ML3|temp2 (|c10:ML3|:13)
- 1 - C 16 DFFE + 1 1 0 9 |c10:ML3|temp1 (|c10:ML3|:14)
- 5 - C 15 DFFE + 1 2 0 9 |c10:ML3|temp0 (|c10:ML3|:15)
- 3 - C 18 OR2 ! 0 4 0 2 |c10:ML3|:77
- 2 - C 15 OR2 ! 0 4 0 3 |c10:ML3|:154
- 8 - C 18 AND2 s 0 2 0 3 |c10:ML3|~238~1
- 7 - C 18 OR2 0 4 0 1 |c10:ML3|:238
- 5 - C 18 OR2 0 4 0 1 |c10:ML3|:239
- 4 - C 16 AND2 s 0 2 0 1 |c10:ML3|~244~1
- 5 - C 16 OR2 0 4 0 1 |c10:ML3|:244
- 3 - C 16 OR2 0 4 0 1 |c10:ML3|:247
- 6 - C 16 OR2 0 4 0 1 |c10:ML3|:248
- 7 - C 16 OR2 0 4 0 1 |c10:ML3|:252
- 8 - C 16 OR2 0 4 0 1 |c10:ML3|:255
- 2 - C 18 OR2 ! 0 2 0 5 |c10:ML3|:329
- 1 - C 15 OR2 ! 0 2 0 3 |c10:ML3|:354
- 1 - C 03 OR2 0 2 0 1 |c10:SL2|LPM_ADD_SUB:102|addcore:adder|:67
- 7 - C 03 OR2 0 3 0 1 |c10:SL2|LPM_ADD_SUB:102|addcore:adder|:68
- 6 - C 09 OR2 0 4 0 1 |c10:SL2|LPM_ADD_SUB:102|addcore:adder|:69
- 3 - C 06 OR2 0 3 0 1 |c10:SL2|LPM_ADD_SUB:179|addcore:adder|:68
- 4 - C 09 OR2 0 4 0 1 |c10:SL2|LPM_ADD_SUB:179|addcore:adder|:69
- 2 - C 09 DFFE + 1 1 0 6 |c10:SL2|temp3 (|c10:SL2|:12)
- 1 - C 06 DFFE + 1 1 0 8 |c10:SL2|temp2 (|c10:SL2|:13)
- 5 - C 03 DFFE + 1 1 0 9 |c10:SL2|temp1 (|c10:SL2|:14)
- 4 - C 03 DFFE + 1 2 0 9 |c10:SL2|temp0 (|c10:SL2|:15)
- 1 - C 09 OR2 ! 0 4 0 4 |c10:SL2|:77
- 3 - C 09 OR2 ! 0 4 0 4 |c10:SL2|:154
- 5 - C 09 OR2 0 4 0 1 |c10:SL2|:231
- 8 - C 09 OR2 0 4 0 1 |c10:SL2|:237
- 8 - C 06 OR2 0 4 0 1 |c10:SL2|:243
- 6 - C 03 OR2 0 4 0 1 |c10:SL2|:246
- 2 - C 03 OR2 0 4 0 1 |c10:SL2|:252
- 3 - C 03 OR2 0 4 0 1 |c10:SL2|:255
- 8 - C 03 OR2 ! 0 2 0 5 |c10:SL2|:329
- 7 - C 09 OR2 ! 0 2 0 4 |c10:SL2|:354
- 3 - C 11 AND2 0 2 0 2 |c10:Ssh1|LPM_ADD_SUB:102|addcore:adder|:55
- 3 - C 07 OR2 0 2 0 1 |c10:Ssh1|LPM_ADD_SUB:102|addcore:adder|:67
- 1 - C 11 OR2 0 3 0 1 |c10:Ssh1|LPM_ADD_SUB:179|addcore:adder|pcarry2
- 5 - C 04 DFFE + 1 2 0 5 |c10:Ssh1|temp3 (|c10:Ssh1|:12)
- 2 - C 04 DFFE + 1 2 0 8 |c10:Ssh1|temp2 (|c10:Ssh1|:13)
- 8 - C 07 DFFE + 1 1 0 8 |c10:Ssh1|temp1 (|c10:Ssh1|:14)
- 2 - C 11 DFFE + 1 2 0 8 |c10:Ssh1|temp0 (|c10:Ssh1|:15)
- 4 - C 11 OR2 ! 0 4 0 4 |c10:Ssh1|:77
- 1 - C 07 OR2 ! 0 4 0 3 |c10:Ssh1|:154
- 4 - C 04 AND2 s 0 2 0 1 |c10:Ssh1|~238~1
- 6 - C 04 OR2 0 4 0 1 |c10:Ssh1|:238
- 1 - C 04 OR2 0 4 0 1 |c10:Ssh1|:239
- 7 - C 07 AND2 s 0 2 0 1 |c10:Ssh1|~244~1
- 4 - C 07 OR2 0 4 0 1 |c10:Ssh1|:244
- 7 - C 04 OR2 0 4 0 1 |c10:Ssh1|:247
- 8 - C 04 OR2 0 4 0 1 |c10:Ssh1|:248
- 2 - C 07 OR2 0 4 0 1 |c10:Ssh1|:252
- 5 - C 07 OR2 0 4 0 1 |c10:Ssh1|:255
- 3 - C 04 OR2 ! 0 2 0 5 |c10:Ssh1|:329
- 6 - C 07 OR2 ! 0 2 0 5 |c10:Ssh1|:354
- 3 - A 02 OR2 0 2 0 1 |c10:Ssl1|LPM_ADD_SUB:102|addcore:adder|:67
- 2 - A 01 OR2 0 4 0 1 |c10:Ssl1|LPM_ADD_SUB:102|addcore:adder|:69
- 3 - A 01 OR2 0 4 0 1 |c10:Ssl1|LPM_ADD_SUB:179|addcore:adder|:69
- 8 - A 01 DFFE + 1 1 0 6 |c10:Ssl1|temp3 (|c10:Ssl1|:12)
- 5 - A 02 DFFE + 1 2 0 8 |c10:Ssl1|temp2 (|c10:Ssl1|:13)
- 2 - A 02 DFFE + 1 1 0 9 |c10:Ssl1|temp1 (|c10:Ssl1|:14)
- 1 - A 06 DFFE + 1 2 0 9 |c10:Ssl1|temp0 (|c10:Ssl1|:15)
- 3 - A 06 OR2 ! 0 2 0 5 |c10:Ssl1|:63
- 4 - A 06 OR2 ! 0 2 0 5 |c10:Ssl1|:67
- 1 - A 01 OR2 ! 0 4 0 4 |c10:Ssl1|:77
- 5 - A 01 OR2 ! 0 4 0 4 |c10:Ssl1|:154
- 6 - A 01 OR2 0 4 0 1 |c10:Ssl1|:231
- 7 - A 01 OR2 0 4 0 1 |c10:Ssl1|:237
- 7 - A 02 AND2 s 0 2 0 1 |c10:Ssl1|~238~1
- 7 - A 06 AND2 s 0 2 0 1 |c10:Ssl1|~244~1
- 8 - A 06 OR2 0 4 0 1 |c10:Ssl1|:244
- 8 - A 02 OR2 0 4 0 1 |c10:Ssl1|:247
- 2 - A 06 OR2 0 4 0 1 |c10:Ssl1|:248
- 4 - A 02 OR2 0 4 0 1 |c10:Ssl1|:252
- 6 - A 02 OR2 0 4 0 1 |c10:Ssl1|:255
- 1 - A 02 OR2 ! 0 2 0 7 |c10:Ssl1|:329
- 4 - A 01 OR2 ! 0 2 0 6 |c10:Ssl1|:354
- 1 - C 23 DFFE + 0 2 1 8 |DLEDDIS:DISPLAY|COUNT2 (|DLEDDIS:DISPLAY|:35)
- 4 - C 23 DFFE + 0 2 1 8 |DLEDDIS:DISPLAY|COUNT1 (|DLEDDIS:DISPLAY|:36)
- 5 - B 17 DFFE + 0 0 1 9 |DLEDDIS:DISPLAY|COUNT0 (|DLEDDIS:DISPLAY|:37)
- 5 - C 23 OR2 ! 0 3 0 4 |DLEDDIS:DISPLAY|:137
- 7 - C 23 AND2 0 3 0 5 |DLEDDIS:DISPLAY|:141
- 8 - C 23 OR2 ! 0 3 0 4 |DLEDDIS:DISPLAY|:145
- 2 - C 23 AND2 0 3 0 4 |DLEDDIS:DISPLAY|:149
- 8 - C 15 OR2 ! 0 3 0 3 |DLEDDIS:DISPLAY|:153
- 7 - C 15 OR2 ! 0 4 0 1 |DLEDDIS:DISPLAY|:178
- 3 - C 10 OR2 ! 0 3 0 1 |DLEDDIS:DISPLAY|:184
- 4 - C 10 OR2 ! 0 3 0 16 |DLEDDIS:DISPLAY|:190
- 4 - C 15 OR2 ! 0 3 0 1 |DLEDDIS:DISPLAY|:196
- 4 - C 06 OR2 ! 0 3 0 1 |DLEDDIS:DISPLAY|:199
- 5 - C 06 OR2 ! 0 3 0 1 |DLEDDIS:DISPLAY|:202
- 6 - C 06 OR2 ! 0 3 0 1 |DLEDDIS:DISPLAY|:205
- 2 - C 06 OR2 ! 0 3 0 16 |DLEDDIS:DISPLAY|:208
- 3 - C 23 AND2 0 4 0 1 |DLEDDIS:DISPLAY|:215
- 6 - C 23 OR2 0 4 0 1 |DLEDDIS:DISPLAY|:216
- 6 - C 08 OR2 0 4 0 1 |DLEDDIS:DISPLAY|:217
- 7 - C 08 OR2 0 3 0 1 |DLEDDIS:DISPLAY|:220
- 8 - C 08 OR2 0 3 0 1 |DLEDDIS:DISPLAY|:223
- 1 - C 08 OR2 0 3 0 16 |DLEDDIS:DISPLAY|:226
- 1 - C 05 AND2 0 2 0 1 |DLEDDIS:DISPLAY|:236
- 6 - C 15 OR2 0 4 0 1 |DLEDDIS:DISPLAY|:237
- 5 - C 11 OR2 0 4 0 1 |DLEDDIS:DISPLAY|:238
- 7 - C 11 AND2 0 2 0 1 |DLEDDIS:DISPLAY|:242
- 6 - C 11 AND2 0 2 0 1 |DLEDDIS:DISPLAY|:243
- 8 - C 11 OR2 0 4 0 15 |DLEDDIS:DISPLAY|:244
- 1 - C 12 AND2 0 4 0 2 |DLEDDIS:DISPLAY|:263
- 6 - C 12 AND2 s ! 0 2 0 1 |DLEDDIS:DISPLAY|~268~1
- 4 - C 12 OR2 ! 0 4 0 2 |DLEDDIS:DISPLAY|:268
- 2 - C 12 AND2 0 4 0 2 |DLEDDIS:DISPLAY|:273
- 3 - C 01 OR2 ! 0 4 0 1 |DLEDDIS:DISPLAY|:283
- 8 - C 01 OR2 ! 0 4 0 1 |DLEDDIS:DISPLAY|:298
- 6 - C 01 OR2 ! 0 4 0 1 |DLEDDIS:DISPLAY|:313
- 7 - C 12 OR2 s 0 4 0 1 |DLEDDIS:DISPLAY|~430~1
- 6 - C 10 OR2 0 4 1 0 |DLEDDIS:DISPLAY|:444
- 4 - C 01 AND2 s 0 3 0 1 |DLEDDIS:DISPLAY|~469~1
- 2 - C 01 OR2 s 0 4 0 1 |DLEDDIS:DISPLAY|~481~1
- 1 - C 10 OR2 0 4 1 0 |DLEDDIS:DISPLAY|:493
- 5 - C 12 OR2 0 4 0 1 |DLEDDIS:DISPLAY|:540
- 8 - C 12 OR2 0 4 1 0 |DLEDDIS:DISPLAY|:544
- 5 - C 01 OR2 0 4 0 1 |DLEDDIS:DISPLAY|:562
- 7 - C 01 OR2 0 3 0 1 |DLEDDIS:DISPLAY|:571
- 1 - C 01 OR2 0 4 0 1 |DLEDDIS:DISPLAY|:588
- 3 - C 12 OR2 0 4 1 0 |DLEDDIS:DISPLAY|:595
- 5 - C 10 OR2 0 4 1 0 |DLEDDIS:DISPLAY|:646
- 2 - C 10 OR2 0 4 1 0 |DLEDDIS:DISPLAY|:697
- 8 - C 10 OR2 0 4 1 0 |DLEDDIS:DISPLAY|:748
- 5 - A 06 AND2 1 0 0 3 |j_t:al|:38
- 6 - A 06 AND2 1 0 0 3 |j_t:al|:47
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\2\dled.rpt
dled
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 29/ 96( 30%) 29/ 48( 60%) 16/ 48( 33%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\2\dled.rpt
dled
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 22 clk1
INPUT 3 clk2
Device-Specific Information: c:\2\dled.rpt
dled
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 25 clr
Device-Specific Information: c:\2\dled.rpt
dled
** EQUATIONS **
clk1 : INPUT;
clk2 : INPUT;
clr : INPUT;
K1 : INPUT;
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