cb10.vhd

来自「数字秒表具有正及时倒计时功能包括一些设计要求和原资料」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CB10 IS
 PORT(CLK: IN STD_LOGIC;
CO: OUT STD_LOGIC);
END CB10;
ARCHITECTURE ART OF CB10 IS
SIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK)
  BEGIN
     IF RISING_EDGE(CLK)THEN
       IF COUNT="1001"THEN 
         COUNT<="0000";
CO<='1';
ELSE
COUNT<=COUNT+1;
CO<='0';
END IF;
END IF;
END PROCESS;
END ART;