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📄 mulx.rpt

📁 数字秒表具有正及时倒计时功能包括一些设计要求和原资料
💻 RPT
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字号:
   -      5     -    C    10        OR2                1    3    0    1  :570
   -      3     -    C    09       AND2                0    4    0    4  :579
   -      1     -    C    04        OR2                1    2    0    1  :582
   -      4     -    C    09       AND2                0    4    0    4  :591
   -      8     -    C    04        OR2                1    2    0    1  :594
   -      7     -    C    11       AND2                0    3    0    4  :603
   -      4     -    C    10        OR2                1    2    0    1  :606
   -      2     -    C    07       AND2                0    4    0    4  :615
   -      7     -    C    10        OR2                1    2    0    1  :618
   -      8     -    C    07       AND2                0    4    0    4  :627
   -      8     -    C    10        OR2                1    2    0    1  :630
   -      6     -    C    07       AND2                0    4    0    4  :639
   -      1     -    C    03        OR2                2    2    0    1  :651
   -      4     -    C    03       AND2                1    3    0    1  :655
   -      2     -    C    03        OR2                0    4    0    1  :656
   -      6     -    C    03        OR2                1    3    0    1  :657
   -      7     -    C    09        OR2                1    2    0    1  :660
   -      6     -    C    09        OR2                1    2    0    1  :663
   -      5     -    C    03        OR2                1    2    0    1  :666
   -      7     -    C    03        OR2                1    2    0    1  :669
   -      8     -    C    03        OR2                1    2    0    1  :672
   -      1     -    C    06        OR2                2    2    0    1  :684
   -      3     -    C    06       AND2                1    3    0    1  :688
   -      2     -    C    06        OR2                0    4    0    1  :689
   -      5     -    C    06        OR2                1    3    0    1  :690
   -      5     -    C    09        OR2                1    2    0    1  :693
   -      8     -    C    09        OR2                1    2    0    1  :696
   -      4     -    C    06        OR2                1    2    0    1  :699
   -      7     -    C    06        OR2                1    2    0    1  :702
   -      8     -    C    06        OR2                1    2    0    1  :705
   -      1     -    C    05        OR2                2    2    0    1  :717
   -      4     -    C    05       AND2                1    3    0    1  :721
   -      3     -    C    05        OR2                0    4    0    1  :722
   -      8     -    C    05        OR2                1    3    0    1  :723
   -      1     -    C    09        OR2                1    2    0    1  :726
   -      2     -    C    09        OR2                1    2    0    1  :729
   -      5     -    C    05        OR2                1    2    0    1  :732
   -      6     -    C    05        OR2                1    2    0    1  :735
   -      7     -    C    05        OR2                1    2    0    1  :738


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                                   c:\new\mulx.rpt
mulx

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     2/ 48(  4%)     0/ 48(  0%)    0/16(  0%)      2/16( 12%)     0/16(  0%)
B:       0/ 96(  0%)     2/ 48(  4%)     0/ 48(  0%)    0/16(  0%)      2/16( 12%)     0/16(  0%)
C:      28/ 96( 29%)    27/ 48( 56%)     0/ 48(  0%)    8/16( 50%)      1/16(  6%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
03:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
04:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
05:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
07:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
10:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
11:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
12:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
17:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
20:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                                   c:\new\mulx.rpt
mulx

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       11         CLK


Device-Specific Information:                                   c:\new\mulx.rpt
mulx

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        4         CLR


Device-Specific Information:                                   c:\new\mulx.rpt
mulx

** EQUATIONS **

CLK      : INPUT;
CLR      : INPUT;
EN       : INPUT;
HOUR0    : INPUT;
HOUR1    : INPUT;
HOUR2    : INPUT;
HOUR3    : INPUT;
M_1MIN0  : INPUT;
M_1MIN1  : INPUT;
M_1MIN2  : INPUT;
M_1MIN3  : INPUT;
M_10MIN0 : INPUT;
M_10MIN1 : INPUT;
M_10MIN2 : INPUT;
M_10MIN3 : INPUT;
S_1MS0   : INPUT;
S_1MS1   : INPUT;
S_1MS2   : INPUT;
S_1MS3   : INPUT;
S_1S0    : INPUT;
S_1S1    : INPUT;
S_1S2    : INPUT;
S_1S3    : INPUT;
S_10MS0  : INPUT;
S_10MS1  : INPUT;
S_10MS2  : INPUT;
S_10MS3  : INPUT;
S_10S0   : INPUT;
S_10S1   : INPUT;
S_10S2   : INPUT;
S_10S3   : INPUT;
S_100MS0 : INPUT;
S_100MS1 : INPUT;
S_100MS2 : INPUT;
S_100MS3 : INPUT;

-- Node name is ':53' = 'COUNT0' 
-- Equation name is 'COUNT0', location is LC5_C11, type is buried.
!COUNT0  = COUNT0~NOT;
COUNT0~NOT = DFFE( _EQ001, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ001 =  COUNT0 &  EN
         # !COUNT0 & !EN;

-- Node name is ':52' = 'COUNT1' 
-- Equation name is 'COUNT1', location is LC6_C11, type is buried.
!COUNT1  = COUNT1~NOT;
COUNT1~NOT = DFFE( _EQ002, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ002 = !COUNT0 & !COUNT1
         # !COUNT1 &  _LC4_C11
         # !COUNT1 & !EN
         #  COUNT0 &  COUNT1 &  EN
         #  EN &  _LC4_C11;

-- Node name is ':51' = 'COUNT2' 
-- Equation name is 'COUNT2', location is LC2_C11, type is buried.
!COUNT2  = COUNT2~NOT;
COUNT2~NOT = DFFE( _EQ003, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ003 = !COUNT2 & !_LC8_C11
         # !COUNT2 &  _LC4_C11
         # !COUNT2 & !EN
         #  EN &  _LC4_C11
         #  COUNT2 &  EN &  _LC8_C11;

-- Node name is ':50' = 'COUNT3' 
-- Equation name is 'COUNT3', location is LC1_C11, type is buried.
!COUNT3  = COUNT3~NOT;
COUNT3~NOT = DFFE( _EQ004, GLOBAL( CLK), GLOBAL(!CLR),  VCC,  VCC);
  _EQ004 = !COUNT3 &  _LC4_C11
         # !COUNT3 & !EN
         # !COUNT3 & !_LC3_C11
         #  EN &  _LC4_C11
         #  EN & !_LC3_C11;

-- Node name is 'OUTBCD0' 
-- Equation name is 'OUTBCD0', type is output 
OUTBCD0  =  _LC2_C5;

-- Node name is 'OUTBCD1' 
-- Equation name is 'OUTBCD1', type is output 
OUTBCD1  =  _LC6_C6;

-- Node name is 'OUTBCD2' 
-- Equation name is 'OUTBCD2', type is output 
OUTBCD2  =  _LC3_C3;

-- Node name is 'OUTBCD3' 
-- Equation name is 'OUTBCD3', type is output 
OUTBCD3  =  _LC6_C10;

-- Node name is 'SEG0' 
-- Equation name is 'SEG0', type is output 
SEG0     =  _LC4_C7;

-- Node name is 'SEG1' 
-- Equation name is 'SEG1', type is output 
SEG1     =  _LC1_C7;

-- Node name is 'SEG2' 
-- Equation name is 'SEG2', type is output 
SEG2     =  _LC7_C7;

-- Node name is '|LPM_ADD_SUB:114|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C11', type is buried 
_LC8_C11 = LCELL( _EQ005);
  _EQ005 =  COUNT0 &  COUNT1;

-- Node name is '|LPM_ADD_SUB:114|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_C11', type is buried 
_LC3_C11 = LCELL( _EQ006);
  _EQ006 = !COUNT2 &  COUNT3
         #  COUNT3 & !_LC8_C11
         #  COUNT2 & !COUNT3 &  _LC8_C11;

-- Node name is ':36' 
-- Equation name is '_LC6_C10', type is buried 
_LC6_C10 = DFFE( _EQ007, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ007 = !_LC6_C7 &  _LC8_C10
         #  _LC6_C7 &  S_1MS3;

-- Node name is ':38' 
-- Equation name is '_LC3_C3', type is buried 
_LC3_C3  = DFFE( _EQ008, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ008 = !_LC6_C7 &  _LC8_C3
         #  _LC6_C7 &  S_1MS2;

-- Node name is ':40' 
-- Equation name is '_LC6_C6', type is buried 
_LC6_C6  = DFFE( _EQ009, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ009 = !_LC6_C7 &  _LC8_C6
         #  _LC6_C7 &  S_1MS1;

-- Node name is ':42' 
-- Equation name is '_LC2_C5', type is buried 
_LC2_C5  = DFFE( _EQ010, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ010 = !_LC6_C7 &  _LC7_C5
         #  _LC6_C7 &  S_1MS0;

-- Node name is ':44' 
-- Equation name is '_LC7_C7', type is buried 
_LC7_C7  = DFFE( _EQ011, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ011 =  COUNT2 & !COUNT3;

-- Node name is ':46' 
-- Equation name is '_LC1_C7', type is buried 
_LC1_C7  = DFFE( _EQ012, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ012 =  COUNT1 & !COUNT3;

-- Node name is ':48' 
-- Equation name is '_LC4_C7', type is buried 
_LC4_C7  = DFFE( _EQ013, GLOBAL( CLK),  VCC,  VCC,  VCC);
  _EQ013 =  COUNT0 & !COUNT1 & !COUNT2
         #  COUNT0 & !COUNT3;

-- Node name is ':89' 
-- Equation name is '_LC4_C11', type is buried 
_LC4_C11 = LCELL( _EQ014);
  _EQ014 =  COUNT0 & !COUNT1 & !COUNT2 &  COUNT3;

-- Node name is ':543' 
-- Equation name is '_LC5_C7', type is buried 
_LC5_C7  = LCELL( _EQ015);
  _EQ015 = !COUNT0 & !COUNT1 & !COUNT2 &  COUNT3;

-- Node name is ':546' 
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = LCELL( _EQ016);
  _EQ016 =  _LC4_C11 &  S_10MS3
         #  _LC5_C7 &  S_1MS3;

-- Node name is ':559' 
-- Equation name is '_LC3_C10', type is buried 
_LC3_C10 = LCELL( _EQ017);
  _EQ017 =  COUNT2 & !COUNT3 &  HOUR3 &  _LC8_C11;

-- Node name is ':560' 
-- Equation name is '_LC2_C10', type is buried 
_LC2_C10 = LCELL( _EQ018);
  _EQ018 = !COUNT2 &  _LC1_C10
         #  _LC1_C10 & !_LC8_C11
         #  COUNT3 &  _LC1_C10;

-- Node name is ':567' 
-- Equation name is '_LC3_C7', type is buried 
_LC3_C7  = LCELL( _EQ019);
  _EQ019 = !COUNT0 &  COUNT1 &  COUNT2 & !COUNT3;

-- Node name is ':570' 
-- Equation name is '_LC5_C10', type is buried 
_LC5_C10 = LCELL( _EQ020);
  _EQ020 =  _LC2_C10 & !_LC3_C7
         # !_LC3_C7 &  _LC3_C10
         #  _LC3_C7 &  M_10MIN3;

-- Node name is ':579' 
-- Equation name is '_LC3_C9', type is buried 
_LC3_C9  = LCELL( _EQ021);

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