mb.rpt
来自「数字秒表具有正及时倒计时功能包括一些设计要求和原资料」· RPT 代码 · 共 1,360 行 · 第 1/5 页
RPT
1,360 行
mb
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 CLK
2 - - - -- INPUT G 0 0 0 0 CLR
42 - - - -- INPUT 0 0 0 2 SP
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\new\mb.rpt
mb
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
22 - - B -- OUTPUT 0 1 0 0 CO
25 - - B -- OUTPUT 0 1 0 0 EN
69 - - A -- OUTPUT 0 1 0 0 LED0
19 - - A -- OUTPUT 0 1 0 0 LED1
72 - - A -- OUTPUT 0 1 0 0 LED2
71 - - A -- OUTPUT 0 1 0 0 LED3
70 - - A -- OUTPUT 0 1 0 0 LED4
73 - - A -- OUTPUT 0 1 0 0 LED5
48 - - - 15 OUTPUT 0 1 0 0 LED6
51 - - - 18 OUTPUT 0 1 0 0 OUTBCD0
80 - - - 23 OUTPUT 0 1 0 0 OUTBCD1
53 - - - 20 OUTPUT 0 1 0 0 OUTBCD2
83 - - - 13 OUTPUT 0 1 0 0 OUTBCD3
67 - - B -- OUTPUT 0 1 0 0 SEG0
64 - - B -- OUTPUT 0 1 0 0 SEG1
66 - - B -- OUTPUT 0 1 0 0 SEG2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\new\mb.rpt
mb
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 15 OR2 0 4 1 0 |BCD7:U4|:135
- 1 - A 15 OR2 0 4 1 0 |BCD7:U4|:168
- 5 - A 15 OR2 0 4 1 0 |BCD7:U4|:201
- 4 - A 15 OR2 0 4 1 0 |BCD7:U4|:234
- 3 - A 15 OR2 0 4 1 0 |BCD7:U4|:267
- 7 - A 15 OR2 0 4 1 0 |BCD7:U4|:300
- 8 - A 15 OR2 0 4 1 0 |BCD7:U4|:335
- 2 - B 08 DFFE + 0 4 1 5 |CB10:U1|:2
- 1 - B 08 DFFE + 0 3 0 2 |CB10:U1|COUNT3 (|CB10:U1|:4)
- 3 - B 08 DFFE + 0 2 0 3 |CB10:U1|COUNT2 (|CB10:U1|:5)
- 4 - B 08 DFFE + 0 3 0 3 |CB10:U1|COUNT1 (|CB10:U1|:6)
- 5 - B 08 DFFE + 0 0 0 4 |CB10:U1|COUNT0 (|CB10:U1|:7)
- 7 - B 16 AND2 0 2 0 1 |COUNT:U2|CDU6:U5|LPM_ADD_SUB:81|addcore:adder|:55
- 8 - B 16 AND2 0 3 0 1 |COUNT:U2|CDU6:U5|LPM_ADD_SUB:81|addcore:adder|:59
- 2 - B 16 DFFE 0 3 0 5 |COUNT:U2|CDU6:U5|:4
- 4 - B 16 DFFE 0 4 0 2 |COUNT:U2|CDU6:U5|SCOUNT63 (|COUNT:U2|CDU6:U5|:10)
- 1 - B 16 DFFE 0 4 0 3 |COUNT:U2|CDU6:U5|SCOUNT62 (|COUNT:U2|CDU6:U5|:11)
- 5 - B 16 DFFE 0 4 0 4 |COUNT:U2|CDU6:U5|SCOUNT61 (|COUNT:U2|CDU6:U5|:12)
- 3 - B 16 DFFE 0 2 0 5 |COUNT:U2|CDU6:U5|SCOUNT60 (|COUNT:U2|CDU6:U5|:13)
- 6 - B 16 AND2 0 4 0 4 |COUNT:U2|CDU6:U5|:54
- 4 - B 17 AND2 0 2 0 1 |COUNT:U2|CDU6:U7|LPM_ADD_SUB:81|addcore:adder|:55
- 8 - B 17 AND2 0 3 0 1 |COUNT:U2|CDU6:U7|LPM_ADD_SUB:81|addcore:adder|:59
- 2 - B 17 DFFE 0 3 0 4 |COUNT:U2|CDU6:U7|:4
- 1 - B 17 DFFE 0 4 0 2 |COUNT:U2|CDU6:U7|SCOUNT63 (|COUNT:U2|CDU6:U7|:10)
- 6 - B 17 DFFE 0 4 0 3 |COUNT:U2|CDU6:U7|SCOUNT62 (|COUNT:U2|CDU6:U7|:11)
- 5 - B 17 DFFE 0 4 0 4 |COUNT:U2|CDU6:U7|SCOUNT61 (|COUNT:U2|CDU6:U7|:12)
- 7 - B 17 DFFE 0 2 0 5 |COUNT:U2|CDU6:U7|SCOUNT60 (|COUNT:U2|CDU6:U7|:13)
- 3 - B 17 AND2 0 4 0 4 |COUNT:U2|CDU6:U7|:54
- 4 - B 09 AND2 0 2 0 1 |COUNT:U2|CDU10:UL|LPM_ADD_SUB:82|addcore:adder|:55
- 7 - B 09 AND2 0 3 0 1 |COUNT:U2|CDU10:UL|LPM_ADD_SUB:82|addcore:adder|:59
- 2 - B 09 DFFE 0 3 0 5 |COUNT:U2|CDU10:UL|:4
- 6 - B 09 DFFE 0 4 0 3 |COUNT:U2|CDU10:UL|SCOUNT103 (|COUNT:U2|CDU10:UL|:10)
- 5 - B 09 DFFE 0 4 0 4 |COUNT:U2|CDU10:UL|SCOUNT102 (|COUNT:U2|CDU10:UL|:11)
- 1 - B 09 DFFE 0 4 0 5 |COUNT:U2|CDU10:UL|SCOUNT101 (|COUNT:U2|CDU10:UL|:12)
- 8 - B 09 DFFE 0 2 0 6 |COUNT:U2|CDU10:UL|SCOUNT100 (|COUNT:U2|CDU10:UL|:13)
- 3 - B 09 AND2 0 4 0 4 |COUNT:U2|CDU10:UL|:54
- 7 - B 12 AND2 0 2 0 1 |COUNT:U2|CDU10:U2|LPM_ADD_SUB:82|addcore:adder|:55
- 8 - B 12 AND2 0 3 0 1 |COUNT:U2|CDU10:U2|LPM_ADD_SUB:82|addcore:adder|:59
- 1 - B 12 DFFE 0 3 0 5 |COUNT:U2|CDU10:U2|:4
- 5 - B 12 DFFE 0 4 0 3 |COUNT:U2|CDU10:U2|SCOUNT103 (|COUNT:U2|CDU10:U2|:10)
- 2 - B 12 DFFE 0 4 0 4 |COUNT:U2|CDU10:U2|SCOUNT102 (|COUNT:U2|CDU10:U2|:11)
- 3 - B 12 DFFE 0 4 0 5 |COUNT:U2|CDU10:U2|SCOUNT101 (|COUNT:U2|CDU10:U2|:12)
- 4 - B 12 DFFE 0 2 0 6 |COUNT:U2|CDU10:U2|SCOUNT100 (|COUNT:U2|CDU10:U2|:13)
- 6 - B 12 AND2 0 4 0 4 |COUNT:U2|CDU10:U2|:54
- 5 - B 04 AND2 0 2 0 1 |COUNT:U2|CDU10:U3|LPM_ADD_SUB:82|addcore:adder|:55
- 7 - B 04 AND2 0 3 0 1 |COUNT:U2|CDU10:U3|LPM_ADD_SUB:82|addcore:adder|:59
- 2 - B 04 DFFE 0 3 0 5 |COUNT:U2|CDU10:U3|:4
- 4 - B 04 DFFE 0 4 0 2 |COUNT:U2|CDU10:U3|SCOUNT103 (|COUNT:U2|CDU10:U3|:10)
- 1 - B 04 DFFE 0 4 0 3 |COUNT:U2|CDU10:U3|SCOUNT102 (|COUNT:U2|CDU10:U3|:11)
- 8 - B 04 DFFE 0 4 0 4 |COUNT:U2|CDU10:U3|SCOUNT101 (|COUNT:U2|CDU10:U3|:12)
- 6 - B 04 DFFE 0 2 0 5 |COUNT:U2|CDU10:U3|SCOUNT100 (|COUNT:U2|CDU10:U3|:13)
- 3 - B 04 AND2 0 4 0 4 |COUNT:U2|CDU10:U3|:54
- 2 - B 15 AND2 0 2 0 1 |COUNT:U2|CDU10:U4|LPM_ADD_SUB:82|addcore:adder|:55
- 3 - B 15 AND2 0 3 0 1 |COUNT:U2|CDU10:U4|LPM_ADD_SUB:82|addcore:adder|:59
- 7 - B 15 DFFE 0 3 0 5 |COUNT:U2|CDU10:U4|:4
- 6 - B 15 DFFE 0 4 0 2 |COUNT:U2|CDU10:U4|SCOUNT103 (|COUNT:U2|CDU10:U4|:10)
- 4 - B 15 DFFE 0 4 0 3 |COUNT:U2|CDU10:U4|SCOUNT102 (|COUNT:U2|CDU10:U4|:11)
- 5 - B 15 DFFE 0 4 0 4 |COUNT:U2|CDU10:U4|SCOUNT101 (|COUNT:U2|CDU10:U4|:12)
- 8 - B 15 DFFE 0 2 0 5 |COUNT:U2|CDU10:U4|SCOUNT100 (|COUNT:U2|CDU10:U4|:13)
- 1 - B 15 AND2 0 4 0 4 |COUNT:U2|CDU10:U4|:54
- 6 - B 14 AND2 0 2 0 1 |COUNT:U2|CDU10:U6|LPM_ADD_SUB:82|addcore:adder|:55
- 8 - B 14 AND2 0 3 0 1 |COUNT:U2|CDU10:U6|LPM_ADD_SUB:82|addcore:adder|:59
- 1 - B 14 DFFE 0 3 0 5 |COUNT:U2|CDU10:U6|:4
- 7 - B 14 DFFE 0 4 0 2 |COUNT:U2|CDU10:U6|SCOUNT103 (|COUNT:U2|CDU10:U6|:10)
- 2 - B 14 DFFE 0 4 0 3 |COUNT:U2|CDU10:U6|SCOUNT102 (|COUNT:U2|CDU10:U6|:11)
- 5 - B 14 DFFE 0 4 0 4 |COUNT:U2|CDU10:U6|SCOUNT101 (|COUNT:U2|CDU10:U6|:12)
- 3 - B 14 DFFE 0 2 0 5 |COUNT:U2|CDU10:U6|SCOUNT100 (|COUNT:U2|CDU10:U6|:13)
- 4 - B 14 AND2 0 4 0 4 |COUNT:U2|CDU10:U6|:54
- 6 - B 22 AND2 0 2 0 1 |COUNT:U2|CDU10:U8|LPM_ADD_SUB:82|addcore:adder|:55
- 7 - B 22 AND2 0 3 0 1 |COUNT:U2|CDU10:U8|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - B 22 DFFE 0 4 0 2 |COUNT:U2|CDU10:U8|SCOUNT103 (|COUNT:U2|CDU10:U8|:10)
- 1 - B 22 DFFE 0 4 0 3 |COUNT:U2|CDU10:U8|SCOUNT102 (|COUNT:U2|CDU10:U8|:11)
- 5 - B 22 DFFE 0 4 0 4 |COUNT:U2|CDU10:U8|SCOUNT101 (|COUNT:U2|CDU10:U8|:12)
- 4 - B 22 DFFE 0 2 0 5 |COUNT:U2|CDU10:U8|SCOUNT100 (|COUNT:U2|CDU10:U8|:13)
- 2 - B 22 OR2 s 0 3 0 1 |COUNT:U2|CDU10:U8|~54~1
- 3 - B 22 OR2 s 0 3 0 3 |COUNT:U2|CDU10:U8|~149~1
- 6 - B 21 DFFE + 1 1 0 1 |CTRL:U0|CURRENT_STATE1 (|CTRL:U0|:5)
- 5 - B 21 DFFE + 1 0 0 2 |CTRL:U0|CURRENT_STATE0 (|CTRL:U0|:6)
- 8 - B 21 OR2 0 2 1 44 |CTRL:U0|:191
- 4 - B 21 AND2 0 2 0 1 |MULX:U3|LPM_ADD_SUB:124|addcore:adder|:55
- 3 - B 21 AND2 0 3 0 5 |MULX:U3|LPM_ADD_SUB:124|addcore:adder|:59
- 5 - B 13 DFFE + 0 3 1 7 |MULX:U3|:36
- 1 - B 19 DFFE + 0 3 1 7 |MULX:U3|:38
- 2 - B 23 DFFE + 0 3 1 7 |MULX:U3|:40
- 4 - B 18 DFFE + 0 3 1 7 |MULX:U3|:42
- 2 - B 24 DFFE + 0 4 1 0 |MULX:U3|:54
- 7 - B 21 DFFE + 0 4 1 0 |MULX:U3|:56
- 1 - B 21 DFFE + 0 4 1 0 |MULX:U3|:58
- 6 - B 20 DFFE + ! 0 3 0 16 |MULX:U3|COUNT3 (|MULX:U3|:60)
- 2 - B 21 DFFE + ! 0 3 0 13 |MULX:U3|COUNT2 (|MULX:U3|:61)
- 4 - B 20 DFFE + ! 0 3 0 14 |MULX:U3|COUNT1 (|MULX:U3|:62)
- 2 - B 02 DFFE + ! 0 1 0 15 |MULX:U3|COUNT0 (|MULX:U3|:63)
- 3 - B 20 AND2 0 4 0 7 |MULX:U3|:99
- 8 - B 20 AND2 0 4 0 4 |MULX:U3|:718
- 2 - B 20 OR2 0 4 0 1 |MULX:U3|:721
- 1 - B 13 OR2 0 4 0 1 |MULX:U3|:733
- 1 - B 24 AND2 0 4 0 4 |MULX:U3|:742
- 2 - B 13 OR2 0 3 0 1 |MULX:U3|:745
- 5 - B 24 AND2 0 4 0 4 |MULX:U3|:754
- 3 - B 13 OR2 0 3 0 1 |MULX:U3|:757
- 3 - B 24 OR2 ! 0 4 0 4 |MULX:U3|:766
- 4 - B 13 OR2 0 3 0 1 |MULX:U3|:769
- 4 - B 24 AND2 0 4 0 4 |MULX:U3|:778
- 6 - B 13 OR2 0 3 0 1 |MULX:U3|:781
- 8 - B 24 AND2 0 4 0 4 |MULX:U3|:790
- 7 - B 13 OR2 0 3 0 1 |MULX:U3|:793
- 7 - B 24 AND2 0 4 0 4 |MULX:U3|:802
- 8 - B 13 OR2 0 3 0 1 |MULX:U3|:805
- 6 - B 24 AND2 0 4 0 4 |MULX:U3|:814
- 1 - B 20 OR2 0 4 0 1 |MULX:U3|:826
- 2 - B 19 OR2 0 4 0 1 |MULX:U3|:829
- 3 - B 19 OR2 0 3 0 1 |MULX:U3|:832
- 4 - B 19 OR2 0 3 0 1 |MULX:U3|:835
- 5 - B 19 OR2 0 3 0 1 |MULX:U3|:838
- 6 - B 19 OR2 0 3 0 1 |MULX:U3|:841
- 7 - B 19 OR2 0 3 0 1 |MULX:U3|:844
- 8 - B 19 OR2 0 3 0 1 |MULX:U3|:847
- 7 - B 20 OR2 0 4 0 1 |MULX:U3|:859
- 1 - B 23 OR2 0 4 0 1 |MULX:U3|:862
- 3 - B 23 OR2 0 3 0 1 |MULX:U3|:865
- 4 - B 23 OR2 0 3 0 1 |MULX:U3|:868
- 5 - B 23 OR2 0 3 0 1 |MULX:U3|:871
- 6 - B 23 OR2 0 3 0 1 |MULX:U3|:874
- 7 - B 23 OR2 0 3 0 1 |MULX:U3|:877
- 8 - B 23 OR2 0 3 0 1 |MULX:U3|:880
- 5 - B 20 OR2 0 4 0 1 |MULX:U3|:892
- 1 - B 18 OR2 0 4 0 1 |MULX:U3|:895
- 2 - B 18 OR2 0 3 0 1 |MULX:U3|:898
- 3 - B 18 OR2 0 3 0 1 |MULX:U3|:901
- 5 - B 18 OR2 0 3 0 1 |MULX:U3|:904
- 6 - B 18 OR2 0 3 0 1 |MULX:U3|:907
- 7 - B 18 OR2 0 3 0 1 |MULX:U3|:910
- 8 - B 18 OR2 0 3 0 1 |MULX:U3|:913
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\new\mb.rpt
mb
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 21/ 96( 21%) 3/ 48( 6%) 37/ 48( 77%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\new\mb.rpt
mb
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 CLK
DFF 6 |CB10:U1|:2
DFF 6 |COUNT:U2|CDU6:U5|:4
DFF 6 |COUNT:U2|CDU10:UL|:4
DFF 6 |COUNT:U2|CDU10:U2|:4
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