mulx.vhd

数字秒表具有正及时倒计时功能包括一些设计要求和原资料

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MULX IS
    PORT ( CLK,CLR,EN:  IN STD_LOGIC;
                S_1MS:     IN STD_LOGIC_VECTOR(3 DOWNTO 0);
               S_10MS:    IN STD_LOGIC_VECTOR(3 DOWNTO 0);
              S_100MS:   IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                 S_1S:      IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                S_10S:     IN STD_LOGIC_VECTOR(3 DOWNTO 0);
               M_1MIN:    IN STD_LOGIC_VECTOR(3 DOWNTO 0);
              M_10MIN:   IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                 HOUR:      IN STD_LOGIC_VECTOR(3 DOWNTO 0);
               OUTBCD:   OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                  SEG:      OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END MULX;
ARCHITECTURE ART OF MULX IS
    SIGNAL  COUNT:STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
    PROCESS(CLK)
    BEGIN
        IF  CLR='1'THEN
            COUNT<="1111";
        ELSIF  RISING_EDGE(CLK) THEN
            IF EN='1' THEN
                IF COUNT="1001" THEN
                    COUNT<="0000";
                ELSE
                    COUNT<=COUNT+'1';
                END  IF;
            END IF;
        END  IF;
    END  PROCESS;
    PROCESS(CLK)
    BEGIN
        IF  CLK'EVENT  AND  CLK='1'THEN
        CASE  COUNT  IS
          WHEN"0000"=>OUTBCD<=S_1MS;    SEG<="000";
          WHEN"0001"=>OUTBCD<=S_10MS;   SEG<="001";
          WHEN"0010"=>OUTBCD<=S_100MS;  SEG<="010";
          WHEN"0011"=>OUTBCD<=S_1S;     SEG<="011";
          WHEN"0100"=>OUTBCD<=S_10S;    SEG<="100";
          WHEN"0101"=>OUTBCD<=M_1MIN;   SEG<="101";
          WHEN"0110"=>OUTBCD<=M_10MIN;  SEG<="110";
          WHEN"0111"=>OUTBCD<=HOUR;     SEG<="111";
          WHEN"1000"=>OUTBCD<=S_1MS;    SEG<="000";
          WHEN"1001"=>OUTBCD<=S_10MS;   SEG<="001";
          WHEN OTHERS=>OUTBCD<="0000";  SEG<="000";
        END CASE;
        END  IF;
    END  PROCESS;
END  ART;