memctrl.v

8051的Verilog实现

      ((instr == ACALL_0 & cycle == 5) |
      (instr == ACALL_1 & cycle == 5) |
      (instr == ACALL_2 & cycle == 5) |
      (instr == ACALL_3 & cycle == 5) |
      (instr == ACALL_4 & cycle == 5) |
      (instr == ACALL_5 & cycle == 5) |
      (instr == ACALL_6 & cycle == 5) |
      (instr == ACALL_7 & cycle == 5) |
      (instr == LCALL & cycle == 5) |
      (instr == RET & cycle == 3) |
      (instr == RETI & cycle == 3) |
      (instr == AJMP_0 & cycle == 2) |
      (instr == AJMP_1 & cycle == 2) |
      (instr == AJMP_2 & cycle == 2) |
      (instr == AJMP_3 & cycle == 2) |
      (instr == AJMP_4 & cycle == 2) |
      (instr == AJMP_5 & cycle == 2) |
      (instr == AJMP_6 & cycle == 2) |
      (instr == AJMP_7 & cycle == 2) |
      (instr == LJMP & cycle == 3)) ? 1'b1
      : 1'b0 ; 
   
   //------------------------------------------------------------------
   // Rel register write enable
   //------------------------------------------------------------------
   assign relwe =
      ((instr == SJMP & cycle == 1) |
      (instr == JZ & cycle == 1) |
      (instr == JNZ & cycle == 1) |
      (instr == JC & cycle == 1) |
      (instr == JNC & cycle == 1) |
      (instr == JB_BIT & cycle == 2) |
      (instr == JNB_BIT & cycle == 2) |
      (instr == CJNE_A_ADDR & cycle == 2) |
      (instr == CJNE_A_N & cycle == 2) |
      (instr == CJNE_R0_N & cycle == 2) |
      (instr == CJNE_R1_N & cycle == 2) |
      (instr == CJNE_R2_N & cycle == 2) |
      (instr == CJNE_R3_N & cycle == 2) |
      (instr == CJNE_R4_N & cycle == 2) |
      (instr == CJNE_R5_N & cycle == 2) |
      (instr == CJNE_R6_N & cycle == 2) |
      (instr == CJNE_R7_N & cycle == 2) |
      (instr == CJNE_IR0_N & cycle == 2) |
      (instr == CJNE_IR1_N & cycle == 2) |
      (instr == DJNZ_R0 & cycle == 1) |
      (instr == DJNZ_R1 & cycle == 1) |
      (instr == DJNZ_R2 & cycle == 1) |
      (instr == DJNZ_R3 & cycle == 1) |
      (instr == DJNZ_R4 & cycle == 1) |
      (instr == DJNZ_R5 & cycle == 1) |
      (instr == DJNZ_R6 & cycle == 1) |
      (instr == DJNZ_R7 & cycle == 1) |
      (instr == DJNZ_ADDR & cycle == 2) |
      (instr == JBC_BIT & cycle == 2)) ? 1'b1
      : 1'b0 ; 

   //------------------------------------------------------------------
   // Program Counter incremented buffer
   //------------------------------------------------------------------
   always @(pc)
   begin : pc_inc_proc
   //------------------------------------------------------------------
   pc_inc = pc + 1'b1 ; 
   end 

   //------------------------------------------------------------------
   // Program Counter added buffer
   //------------------------------------------------------------------
   always @(pc or accreg)
   begin : pc_add_hand
   //------------------------------------------------------------------
   pc_add = pc + accreg ; 
   end 

   //------------------------------------------------------------------
   // Program Counter Relative added buffer
   //------------------------------------------------------------------
   always @(pc or rel)
   begin : pc_rel_hand
   //------------------------------------------------------------------
   pc_rel = pc + {rel[7], rel[7], rel[7], rel[7],
                  rel[7], rel[7], rel[7], rel[7], rel}; 
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : pc_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      pc <= ADDR_RV;
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (pcince)       // PC=PC+1
         begin
         pc <= pc_inc ; 
         end
      else if (pcrele)  // PC=PC+rel
         begin
         pc <= pc_rel ; 
         end
      else if (dpadde)  // PC=DPTR+A
         begin
         if (~dps[0])
            begin
            pc <= dp_add;
            end
         else
            begin
            pc <= dp1_add;
            end
         end
      else if (buffsel) // PC=Buffer
         begin
         pc <= addrbuff ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Data Pointer incremented buffer
   //------------------------------------------------------------------
   always @(dptr)
   begin : dp_inc_proc
   //------------------------------------------------------------------
   dp_inc = dptr + 1'b1 ; 
   end 

   //------------------------------------------------------------------
   // Data Pointer 1 incremented buffer
   //------------------------------------------------------------------
   always @(dptr1)
   begin : dp1inc_proc
   //------------------------------------------------------------------
   dp1_inc = dptr1 + 1'b1;
   end

   //------------------------------------------------------------------
   // Data Pointer added buffer
   //------------------------------------------------------------------
   always @(dptr or accreg)
   begin : dp_add_hand
   //------------------------------------------------------------------
   dp_add = dptr + accreg ; 
   end 

   //------------------------------------------------------------------
   // Data Pointer 1 added buffer
   //------------------------------------------------------------------
   always @(dptr1 or accreg)
   begin : dp1_add_hand
   //------------------------------------------------------------------
   dp1_add = dptr1 + accreg;
   end

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : dp_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      dptr[7:0]  <= DPL_RV ; 
      dptr[15:8] <= DPH_RV ; 
      dptr1[7:0]  <= DPL1_RV;
      dptr1[15:8] <= DPH1_RV;
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Data Pointer increment or load
      //--------------------------------
      begin
      if (dpince)    // DPTR=DPTR+1
         begin
         if (~dps[0])   // DPTR select
            begin
            dptr <= dp_inc ; 
            end
         else
            begin
            dptr1 <= dp1_inc ; 
            end
         end
      else if (dplwe)
         begin
         if (~dps[0])   // DPTR select
            begin
            dptr[7:0] <= memdatai ; 
            end
         else
            begin
            dptr1[7:0] <= memdatai ; 
            end
         end
      else if (dphwe)
         begin
         if (~dps[0])   // DPTR select
            begin
            dptr[15:8] <= memdatai ; 
            end
         else
            begin
            dptr1[15:8] <= memdatai ; 
            end
         end
      else
         //--------------------------------
         // Special function register write
         //--------------------------------
         begin
         if (sfrwe & sfraddr == DPL_ID)
            begin
            dptr[7:0] <= sfrdatai ; 
            end 
         
         if (sfrwe & sfraddr == DPH_ID)
            begin
            dptr[15:8] <= sfrdatai ; 
            end 
            
         if (sfrwe & sfraddr == DPL1_ID)
            begin
            dptr1[7:0] <= sfrdatai ; 
            end 
         
         if (sfrwe & sfraddr == DPH1_ID)
            begin
            dptr1[15:8] <= sfrdatai ; 
            end 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : dps_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      dps[7:0] <= DPS_RV;
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr==DPS_ID)
         begin
         dps[7:0] <= sfrdatai;
         end
      end
   end

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : memaddr_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      memaddr <= ADDR_RV;
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (pcince)          // ADDR=PC+1
         begin
         memaddr <= pc_inc ; 
         end
      else if (pcrele)     // ADDR=PC+rel
         begin
         memaddr <= pc_rel ; 
         end
      else if (pcaddsel)   // ADDR=PC+A
         begin
         memaddr <= pc_add ; 
         end
      else if (dpaddsel)   // ADDR=DPTR+A
         begin
         if (~dps[0])
            begin
            memaddr <= dp_add;
            end
         else
            begin
            memaddr <= dp1_add;
            end
         end
      else if (dpsel)      // ADDR=DPTR
         begin
         if (~dps[0])
            begin
            memaddr <= dptr ; 
            end
         else
            begin
            memaddr <= dptr1 ; 
            end
         end
      else if (risel)      // ADDR(low)=Ri
         begin
         if (cycle == 1)
         // if (stretchcount == 4'b0000)    
            begin
            memaddr[7:0] <= ramdatai ;
            if (ADDR_HIGH_P2_SEL == 0)
               begin
               memaddr[15:8] <= p2reg ;
               end
            else
               begin 
               memaddr[15:8] <= ADDR_HIGH_RI ;
               end
            end
         end
      else if (buffsel)    // ADDR=Buffer
         begin
         memaddr <= addrbuff ; 
         end
      else                 // ADDR=PC
         begin
         memaddr <= pc ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : rel_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      rel <= 8'b00000000 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Relative address register write
      //--------------------------------
      begin
      if (relwe)
         begin
         rel <= memdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : buff_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------