serial1.v

8051的Verilog实现

      begin
      if (!rxd1i)
         begin
         rxd1_inff <= 1'b0 ; 
         end
      else
         begin
         rxd1_inff <= 1'b1 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Falling edge detection on the external input rxd0i
   // rxd1_fall is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : rxd1_fall_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      rxd1_fall <= 1'b0 ; 
      rxd1_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (!rxd1_inff & rxd1_ff)
         begin
         rxd1_fall <= 1'b1 ; 
         end
      else
         begin
         rxd1_fall <= 1'b0 ; 
         end 
      
      //--------------------------------
      // t0 input flip-flop
      //--------------------------------
      rxd1_ff <= rxd1_inff ; 
      
      end  
   end 

   //------------------------------------------------------------------
   // rxd1i input pin falling edge detector
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : rxd1_vec_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      rxd1_vec <= 3'b111 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // RXD vector write
      //--------------------------------
      begin
      if (b1_clk)
         begin
         rxd1_vec <= {rxd1_vec[1:0], rxd1_inff} ; 
         end 
      
      //--------------------------------
      // rxd0i pin value
      //--------------------------------
      if (rxd1_vec == 3'b001 |
          rxd1_vec == 3'b010 |
          rxd1_vec == 3'b100 |
          rxd1_vec == 3'b000)
         begin
         rxd1_val <= 1'b0 ; 
         end
      else
         begin
         rxd1_val <= 1'b1 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Rising edge detection on the r_start 
   // r_start_rise is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : r_start_rise_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      r1_start_rise <= 1'b0 ; 
      r1_start_ff <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      //--------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (r1_start & !r1_start_ff)
         begin
         r1_start_rise <= 1'b1 ; 
         end
      else
         begin
         r1_start_rise <= 1'b0 ; 
         end 
      
      //--------------------------------
      // r_start flip-flop
      //--------------------------------
      r1_start_ff <= r1_start ; 
      
      end  
   end 

   //------------------------------------------------------------------
   // Falling edge detection on the r_start 
   // r_start_fall is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : r_start_fall_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      r1_start_fall <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Falling edge detection
      //--------------------------------
      begin
      if (!r1_start & r1_start_ff)
         begin
         r1_start_fall <= 1'b1 ; 
         end
      else
         begin
         r1_start_fall <= 1'b0 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : receive_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      s1buf_r <= S1BUF_RV ; 
      r1_baud_count <= 4'b0000 ; 
      receive1 <= 1'b0 ; 
      r1_shift_reg <= 11'b11111111111 ; 
      r1_shift_count <= 4'b0000 ; 
      r1_start <= 1'b0 ; 
      r1_start_ok <= 1'b0 ; 
      end
   else
      begin
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Receive clk divide by 16
      //--------------------------------
      if (rxd1_fall & !r1_start)
         begin
         r1_baud_count <= 4'b0000 ; 
         end
      else if (b1_clk)
         begin
         r1_baud_count <= r1_baud_count + 1'b1 ; 
         end 
      
      //--------------------------------
      // Receive register shift
      //--------------------------------
      if (s1con[7])  //Mode A 
         begin
         if (r1_baud_count == 4'b1001 &
             b1_clk &
             r1_start &
             ~(r1_shift_count == 4'b0000))
            begin
            r1_shift_reg[9:0] <= r1_shift_reg[10:1] ; 
            r1_shift_reg[10] <= rxd1_val ; 
            r1_shift_count <= r1_shift_count - 1'b1 ; 
            if (r1_shift_count == 4'b0001)
               begin
               r1_start <= 1'b0 ; 
               receive1 <= 1'b0 ; 
               end 
            
            if (r1_shift_count == 4'b1010)
               begin
               if (!rxd1_val)
                  begin
                  r1_start_ok <= 1'b1 ; 
                  end
               else
                  begin
                  r1_start <= 1'b0 ; 
                  receive1 <= 1'b0 ; 
                  r1_shift_count <= 4'b0000 ; 
                  end 
               end 
            
            end 
            
         if (r1_start_fall & r1_start_ok)
            begin
            r1_start_ok <= 1'b0 ; 
            end 
         
         end
         
      else  //Mode B
         begin
         if (r1_baud_count == 4'b1001 &
             b1_clk &
             receive1 &
             ~(r1_shift_count == 4'b0000))
            begin
            r1_shift_reg[9:0] <= r1_shift_reg[10:1] ; 
            r1_shift_reg[10] <= rxd1_val ; 
            r1_shift_count <= r1_shift_count - 1'b1 ; 
            if (r1_shift_count == 4'b0010)
               begin
               r1_start <= 1'b0 ; 
               end 
            
            if (r1_shift_count == 4'b0001)
               begin
               receive1 <= 1'b0 ; 
               end 
            
            if (r1_shift_count == 4'b1011)
               begin
               if (!rxd1_val)
                  begin
                  r1_start_ok <= 1'b1 ; 
                  end
               else
                  begin
                  r1_start <= 1'b0 ; 
                  receive1 <= 1'b0 ; 
                  r1_shift_count <= 4'b0000 ; 
                  end 
               end 
            end 
         
         if (r1_start_fall & r1_start_ok)
            begin
               r1_start_ok <= 1'b0 ; 
            end 
         end 
         
      if (clk1_count == 4'b1011 & r1_start)
         begin
         if (!receive1)
            begin
            receive1 <= 1'b1 ; 
            end 
         end 
      
      //--------------------------------
      // Receive shift enable
      //--------------------------------
      if (rxd1_fall &
         (s1con[4]) &
         r1_shift_count == 4'b0000)
         begin
         r1_start <= 1'b1 ; 
         end 
      
      if (r1_start_rise & r1_shift_count == 4'b0000)
         begin
         //--------------------------------
         // Receive count load
         //--------------------------------
         if ((s1con[7]))
            begin
            r1_shift_count <= 4'b1010 ; 
            end
         else
            begin
            r1_shift_count <= 4'b1011 ; 
            end 
         end 
   
      if (r1_start_fall)
         begin
         if (r1_start_ok & !(s1con[0]))
            begin
            if (s1con[5])
               begin
               if (r1_shift_reg[10])
                  begin
                  s1buf_r <= r1_shift_reg[9:2] ; 
                  end 
               end
            else
               begin
               s1buf_r <= r1_shift_reg[9:2] ; 
               end 
            end 
         end 
      end  
   end 
   //------------------------------------------------------------------
   // Special Function registers read
   //------------------------------------------------------------------
   assign sfrdataser1 =
      (sfraddr == S1CON_ID) ? s1con :
      (sfraddr == S1BUF_ID) ? s1buf_r :
      (sfraddr == S1RELL_ID) ? s1rell :
      (sfraddr == S1RELH_ID) ? s1relh :
      "--------" ; 


endmodule  //  module SERIAL_1

//*******************************************************************--