serial1.v

8051的Verilog实现

   reg      r1_start_ff; 
   reg      receive1; 
   reg      r1_start_ok; 
   
   // Baud Rate Generator Reload register
   reg      [7:0] s1rell; 
   reg      [7:0] s1relh; 
   
   // Baud Rate Timer
   reg      [9:0] tim1_baud; 

   //------------------------------------------------------------------
   // Serial 1 receive flag
   //   interrupt request flag
   //   high active output
   //------------------------------------------------------------------
   assign ri1 = s1con[0] ; 
   
   //------------------------------------------------------------------
   // Serial 1 transmit flag
   //   interrupt request flag
   //   high active output
   //------------------------------------------------------------------
   assign ti1 = s1con[1] ; 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : s1con_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      s1con <= S1CON_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == S1CON_ID)
         begin
         s1con <= sfrdatai ; 
         end
      else
         begin
         if (t1_shift_clk & t1_shift_count == 4'b0001)
            begin
            s1con[1] <= 1'b1 ; // transmit interrupt flag              
            end 
         
         if (r1_start_fall & r1_start_ok)
            begin
            s1con[2] <= rxd1_val ; 
            if (s1con[5])
               begin
               s1con[0] <= rxd1_val ; // rec. int. flag 
               end
            else
               begin
               s1con[0] <= 1'b1 ;     // rec. int. flag                   
               end 
            end 
         
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : s1rell_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      s1rell <= S1RELL_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == S1RELL_ID)
         begin
         s1rell <= sfrdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : s1relh_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      s1relh <= S1RELH_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == S1RELH_ID)
         begin
         s1relh <= sfrdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   // Timer Baud Rate overflow
   // baud_rate_ov is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : baud1_rate_overflow
   //------------------------------------------------------------------
   //-----------------------------------
   // Synchronous write
   //-----------------------------------
   if (clk1_ov2 & tim1_baud[9:0] == 10'b1111111111)
      begin
      b1_clk <= 1'b1 ; 
      end
   else
      begin
      b1_clk <= 1'b0 ; 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : tim1_baud_reload
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      tim1_baud <= 10'b1111101111 ; // this value is not specified
                                    // in instruction SAB80C517
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      begin
      if (b1_clk)
         begin
         tim1_baud[7:0] <= s1rell ; 
         tim1_baud[9:8] <= s1relh[1:0] ; 
         end
      else if (!clk1_ov2)
         begin
         tim1_baud <= tim1_baud + 1'b1 ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : clk1_count_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      clk1_count <= 4'b0000 ; 
      clk1_ov2 <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // clk counter
      //--------------------------------
      begin
      if (clk1_count == 4'b1011)
         begin
         clk1_count <= 4'b0000 ; 
         end
      else
         begin
         clk1_count <= clk1_count + 1'b1 ; 
         end 
      
      //--------------------------------
      // clk divide by 2
      //--------------------------------
      if (clk1_count[0])
         begin
         clk1_ov2 <= 1'b1 ; 
         end
      else
         begin
         clk1_ov2 <= 1'b0 ; 
         end 
      end  
   end 
   
   //------------------------------------------------------------------
   assign t1_shift_clk =
      (t1_start) ? t1_baud_ov :
      1'b0 ; 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : transmit_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      t1_start <= 1'b0 ; 
      t1_baud_count <= 4'b0000 ; 
      t1_baud_ov <= 1'b0 ; 
      t1_shift_reg <= 11'b11111111111 ; 
      t1_shift_count <= 4'b0000 ; 
      txd1 <= 1'b1 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Transmit clk divide by 16
      //--------------------------------
      begin
      if (b1_clk)
         begin
         t1_baud_count <= t1_baud_count + 1'b1 ; 
         end 
      
      if (b1_clk & t1_baud_count == 4'b1111)
         begin
         t1_baud_ov <= 1'b1 ; 
         end
      else
         begin
         t1_baud_ov <= 1'b0 ; 
         end 
      
      //--------------------------------
      // Transmit shift enable
      //--------------------------------
      if (t1_shift_count == 4'b0000 &
         ~(sfrwe & sfraddr == S1BUF_ID))
         begin
         t1_start <= 1'b0 ; 
         end
      else if (sfrwe & sfraddr == S1BUF_ID)
         begin
         t1_start <= 1'b1 ; 
         end 
      
      //--------------------------------
      // Transmit registers load
      //--------------------------------
      if (sfrwe & sfraddr == S1BUF_ID)
         begin
         case (s1con[7])
         //-------------------------------
         // Mode B
         //-------------------------------
         1'b1 :
            begin
            t1_shift_reg[10] <= 1'b1 ; 
            t1_shift_reg[9:2] <= sfrdatai ; 
            t1_shift_reg[1] <= 1'b0 ; 
            t1_shift_reg[0] <= 1'b1 ; 
            t1_shift_count <= 4'b1010 ; 
            end
         
         //-------------------------------
         // Mode A
         //-------------------------------
         default :
            begin
            t1_shift_reg[10] <= s1con[3] ; 
            t1_shift_reg[9:2] <= sfrdatai ; 
            t1_shift_reg[1] <= 1'b0 ; 
            t1_shift_reg[0] <= 1'b1 ; 
            t1_shift_count <= 4'b1011 ; 
            end
         
         endcase 
         end
      else
         //--------------------------------
         // Transmit register shift
         //--------------------------------
         begin
         if (t1_shift_clk)
            begin
            t1_shift_reg[9:0] <= t1_shift_reg[10:1] ; 
            end 
         
         //--------------------------------
         // Transmit data count
         //--------------------------------
         if (t1_shift_clk)
            begin
            t1_shift_count <= t1_shift_count - 1'b1 ; 
            end 
         end 
         
      //--------------------------------
      // Transmit output
      //--------------------------------
      if (t1_start | r1_start)
         begin
         txd1 <= t1_shift_reg[0] ; 
         end
      else
         begin
         txd1 <= 1'b1 ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   // Flip-flop on rxd1i input
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : rxd1_inff_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      rxd1_inff <= 1'b1 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------