timer.v

8051的Verilog实现

   //------------------------------------------------------------------
   // Timer 1 overflow flag
   //   interrupt request flag
   //   high active output
   //   cleared by high on signal t1ack
   //------------------------------------------------------------------
   assign tf1 = tcon[7] ; 
   
   //------------------------------------------------------------------
   // Interrupt 0 edge detect
   //   interrupt request flag
   //   high active output
   //------------------------------------------------------------------
   assign ie0 = tcon[1] ; 
   
   //------------------------------------------------------------------
   // Interrupt 0 edge/low level selector
   //------------------------------------------------------------------
   assign it0 = tcon[0];
      
   //------------------------------------------------------------------
   // Interrupt 1 edge/low level selector
   //------------------------------------------------------------------
   assign it1 = tcon[2];

   //------------------------------------------------------------------
   // Interrupt 1 edge detect
   //   interrupt request flag
   //   high active output
   //------------------------------------------------------------------
   assign ie1 = tcon[3] ; 
   
   //------------------------------------------------------------------
   // Timer 0 overflow output
   //   output for serial interface
   //   high active output
   //   active during single clk period
   //------------------------------------------------------------------
   //   assign t0ov = th0_ov;
   
   //------------------------------------------------------------------
   // Timer 1 overflow output
   //   output for serial interface
   //   high active output
   //   active during single clk period
   //------------------------------------------------------------------
   assign t1ov = (t1_mode == 2'b10) ? tl1_ov : th1_ov ; 
   
   //------------------------------------------------------------------
   // Timer 0 mode
   //------------------------------------------------------------------
   assign t0_mode = tmod[1:0] ; 
   
   //------------------------------------------------------------------
   // Timer 1 mode
   //------------------------------------------------------------------
   assign t1_mode = tmod[5:4] ; 

   //------------------------------------------------------------------
   // counter 0 mode
   //------------------------------------------------------------------
   assign cnt0_mode = tmod[2];
                            
   //------------------------------------------------------------------
   // counter 1 mode
   //------------------------------------------------------------------
   assign cnt1_mode = tmod[6];
                               
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : tcon_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      tcon <= TCON_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == TCON_ID)
         begin
         tcon <= sfrdatai ; 
         end
      else
         //--------------------------------
         // Interrupt 0 edge/level detect
         //-------------------------------- 
         begin
         if (!(tcon[0]))   // Low level detect
            begin
            tcon[1] <= ~int0 ; 
            end
         else
            begin
            if (int0ack)   // clear int. request
               begin
               tcon[1] <= 1'b0 ; 
               end
            else
               begin
               if (
                     int0_fall |
                     (!int0_ff0 & int0_ff)
                  ) //Falling edge
                  begin
                  tcon[1] <= 1'b1 ; 
                  end 
               end 
            end 
            
         //--------------------------------
         // Interrupt 1 edge/level detect
         //--------------------------------    
         if (!(tcon[2]))   // Low level detect
            begin
            tcon[3] <= ~int1 ; 
            end
         else
            begin
            if (int1ack)   // clear int. request
               begin
               tcon[3] <= 1'b0 ; 
               end
            else
               begin
               if (
                     int1_fall |
                     (!int1_ff0 & int1_ff)
                  )  //Falling edge
                  begin
                  tcon[3] <= 1'b1 ; 
                  end 
               end 
            end 
            
         //--------------------------------
         // Timer 0 interrupt acknoledge
         //--------------------------------
         if (t0ack)
            begin
            tcon[5] <= 1'b0 ; 
            end
         else
            //--------------------------------
            // Timer 0 overflow flag TF0
            //--------------------------------
            begin
            if (
                  (
                     (t0_mode == 2'b00 | t0_mode == 2'b01) &
                     (th0_ov | th0_ov_ff)
                  ) |
                  (
                     (t0_mode == 2'b10 | t0_mode == 2'b11) &
                     (tl0_ov | tl0_ov_ff)
                  )
               )
               begin
               tcon[5] <= 1'b1 ; 
               end 
            end 
            
         //--------------------------------
         // Timer 1 interrupt acknoledge
         //--------------------------------
         if (t1ack)
            begin
            tcon[7] <= 1'b0 ; 
            end
         else
            //--------------------------------
            // Timer 1 overflow flag TF1
            //--------------------------------
            begin
            if (
                  (
                     (t1_mode == 2'b00 | t1_mode == 2'b01) &
                     (th1_ov | th1_ov_ff)
                  ) |
                  (
                     (t1_mode == 2'b10) &
                     (tl1_ov | tl1_ov_ff)
                  ) |
                  (
                  (t0_mode == 2'b11) &
                  (th0_ov | th0_ov_ff)
                  )
               )
               begin
               tcon[7] <= 1'b1 ; 
               end 
            end 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : tmod_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      tmod <= TMOD_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == TMOD_ID)
         begin
         tmod <= sfrdatai ; 
         end 
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : timer0_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      tl0 <= TL0_RV ; 
      th0 <= TH0_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == TL0_ID)
         begin
         if (t0_mode == 2'b00)
           begin
           tl0[7:5] <= 3'b000;
           tl0[4:0] <= sfrdatai[4:0];
           end
         else
           begin
           tl0 <= sfrdatai;
           end
         end 
      else if (t0_mode == 2'b10 & tl0_ov)
         begin
         tl0 <= th0 ; // Reload mode
         end
      else
         begin
         if (tl0_clk)
            begin
            if (t0_mode == 2'b00)
              begin
              tl0[4:0] <= tl0[4:0] + 1'b1;
              end
            else
              begin
              tl0 <= tl0 + 1'b1 ; 
              end
            end 
         end 

      if (sfrwe & sfraddr == TH0_ID)
         begin
         th0 <= sfrdatai ; 
         end 
      else if (th0_clk)
         begin
         th0 <= th0 + 1'b1 ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   always @(posedge clk)
   begin : timer1_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      tl1 <= TL1_RV ; 
      th1 <= TH1_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      //--------------------------------
      // Special function register write
      //--------------------------------
      begin
      if (sfrwe & sfraddr == TL1_ID)
         begin
         if (t1_mode == 2'b00)
           begin
           tl1[7:5] <= 3'b000;
           tl1[4:0] <= sfrdatai[4:0];
           end
         else
           begin
           tl1 <= sfrdatai;
           end
         end 
      else if (t1_mode == 2'b10 & tl1_ov)
         begin
         tl1 <= th1 ; // Reload mode
         end
      else
         begin
         if (tl1_clk)
            begin
            if (t1_mode == 2'b00)
              begin
              tl1[4:0] <= tl1[4:0] + 1'b1;
              end
            else
              begin
              tl1 <= tl1 + 1'b1 ; 
              end
            end 
         end 
      
      if (sfrwe & sfraddr == TH1_ID)
         begin
         th1 <= sfrdatai ; 
         end 
      else if (th1_clk & ~(t1_mode == 2'b10))
         begin
         th1 <= th1 + 1'b1 ; 
         end 
      
      end  
   end 

   //------------------------------------------------------------------
   // Clock counter with overflow divided by 2 or 12
   // clk_ov2 is high active during single clk period
   // clk_ov12 is high active during single clk period
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : clk_count_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      clk_count <= 4'b0000 ; 
      clk_ov12 <= 1'b0 ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Clock counter
      //--------------------------------
      begin
      if (clk_count == 4'b1011)
         begin
         clk_count <= 4'b0000 ; 
         end
      else
         begin
         clk_count <= clk_count + 1'b1 ; 
         end