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//*******************************************************************--
// Copyright (c) 1999-2003 Evatronix SA --
//*******************************************************************--
// Please review the terms of the license agreement before using --
// this file. If you are not an authorized user, please destroy this --
// source code file and notify Evatronix SA immediately that you --
// inadvertently received an unauthorized copy. --
//*******************************************************************--
//---------------------------------------------------------------------
// Project name : R80515
// Project description : R80515 Microcontroller Unit
//
// File name : isr.v
// File contents : Module ISR
// Purpose : Interrupt service routine unit
//
// Destination library : R80515_LIB
//
// Design Engineer : D.K.
// Quality Engineer : M.B.
// Version : 1.15.V04
// Last modification : 2003-04-14
//---------------------------------------------------------------------
`timescale 1 ns / 1 ns // timescale for following modules
//*******************************************************************--
// Modifications with respect to Version 1.01.E00 :
// 1.01.E01 :
// 1999-11-24 : Removed l0 signal from sensitivity list of
// : is_reg_comb_proc:
// 1.04.E00 :
// 2000-04-10 : Multiplexed external interrupt and CCU interrupt
// : Added inputs ccenreg, codefetche
// : Removed input wdtclr
// : Modified ien1_write proc: ien1(6) - stuck at zero
// : Modified ien0_write proc: ien0(6)
// : Modified sfr_read: ien0(6) - always read zero
// 2000-04-26 : Added instr and codefetche ports
// : Removed flip_flop from Interrupt Request Comparator
// : Interrupt Req. Comp. disabled during ISR register access
// : int_vect_sync_proc: int_vect sampled at codefetche
// 2000-04-27 : The t0ack_sync_proc: t1ack_sync_proc: modified to avoid
// : clearing the tf0, tf1 flags in case the intreq is
// : active and interrupt with higher priority comes
// 1.04.E04 :
// 2000-09-25 : Added cycle port
// 2000-09-25 : ircon_write_proc: modified setting ext. int. flags
// 1.04.E05 :
// 2001-01-06 : Removed hardcoded values from ircon_write_proc
// 1.04.E06 :
// 2001-05-10 : Added flip-flips int2_p0-int6_p0 between inputs
// : int2-int6 and flip-flops int2_p2-int6_p2
// 2001-05-10 : Added registers for current priority level signals
// : l0-l3
// 1.10.E00 :
// 2001-09-03 : Added output ports: intprior0, intprior1, eal, eint0,
// : eint1, isreg
// : Added timer 2 overflow flip-flop
// 1.11.E00 :
// 2002-04-04 : Added On-Chip Debug Support related logic
// 2002-04-04 : Added debugfetche, debugreq, a5instr ports
// 1.11.V02 :
// 2002-08-09 : Modified ip0, int_vect, is_reg reset value from
// : hard-coded value on constant
//*******************************************************************--
module ISR
(clk,
rst,
cycle,
instr,
codefetche,
debugfetche,
debugreq,
a5instr,
tf0,
ie0,
tf1,
ie1,
tf2,
exf2,
int2,
int3,
int4,
int5,
int6,
com0,
com1,
com2,
com3,
ccenreg,
ri0,
ti0,
ri1,
ti1,
iadc,
i2fr,
i3fr,
wdts,
intret,
intack,
intprior0,
intprior1,
eal,
eint0,
eint1,
etm0,
etm1,
etm2,
esrl0,
esrl1,
t0ack,
t1ack,
int0ack,
int1ack,
wdt,
intvect,
intreq,
isreg,
sfrdatai,
sfrdataisr,
sfraddr,
sfrwe);
// Declarations
//`include "utility.v"
//------------------------------------------------------------------
//---------------------------------------------------------------
// Special Function Register locations
//---------------------------------------------------------------
// 80h - 87h
parameter[6:0] P0_ID = 7'b0000000;
parameter[6:0] SP_ID = 7'b0000001;
parameter[6:0] DPL_ID = 7'b0000010;
parameter[6:0] DPH_ID = 7'b0000011;
parameter[6:0] DPL1_ID = 7'b0000100;
parameter[6:0] DPH1_ID = 7'b0000101;
parameter[6:0] PCON_ID = 7'b0000111;
parameter[6:0] WDTREL_ID = 7'b0000110;
// 88h - 8Fh
parameter[6:0] TCON_ID = 7'b0001000;
parameter[6:0] TMOD_ID = 7'b0001001;
parameter[6:0] TL0_ID = 7'b0001010;
parameter[6:0] TL1_ID = 7'b0001011;
parameter[6:0] TH0_ID = 7'b0001100;
parameter[6:0] TH1_ID = 7'b0001101;
parameter[6:0] CKCON_ID = 7'b0001110;
// 90h - 97h
parameter[6:0] P1_ID = 7'b0010000;
parameter[6:0] DPS_ID = 7'b0010010;
// 98h - 9Fh
parameter[6:0] S0CON_ID = 7'b0011000;
parameter[6:0] S0BUF_ID = 7'b0011001;
parameter[6:0] IEN2_ID = 7'b0011010;
parameter[6:0] S1CON_ID = 7'b0011011;
parameter[6:0] S1BUF_ID = 7'b0011100;
parameter[6:0] S1RELL_ID = 7'b0011101;
// A0h - A7h
parameter[6:0] P2_ID = 7'b0100000;
// A8h - AFh
parameter[6:0] IEN0_ID = 7'b0101000;
parameter[6:0] IP0_ID = 7'b0101001;
parameter[6:0] S0RELL_ID = 7'b0101010;
// B0h - B7h
parameter[6:0] P3_ID = 7'b0110000;
// B8h - BFh
parameter[6:0] IEN1_ID = 7'b0111000;
parameter[6:0] IP1_ID = 7'b0111001;
parameter[6:0] S0RELH_ID = 7'b0111010;
parameter[6:0] S1RELH_ID = 7'b0111011;
// C0h - C7h
parameter[6:0] IRCON_ID = 7'b1000000;
parameter[6:0] CCEN_ID = 7'b1000001;
parameter[6:0] CCL1_ID = 7'b1000010;
parameter[6:0] CCH1_ID = 7'b1000011;
parameter[6:0] CCL2_ID = 7'b1000100;
parameter[6:0] CCH2_ID = 7'b1000101;
parameter[6:0] CCL3_ID = 7'b1000110;
parameter[6:0] CCH3_ID = 7'b1000111;
// C8h - CFh
parameter[6:0] T2CON_ID = 7'b1001000;
parameter[6:0] T2MOD_ID = 7'b1001001;
parameter[6:0] CRCL_ID = 7'b1001010;
parameter[6:0] CRCH_ID = 7'b1001011;
parameter[6:0] TL2_ID = 7'b1001100;
parameter[6:0] TH2_ID = 7'b1001101;
// D0h - D7h
parameter[6:0] PSW_ID = 7'b1010000;
// D8h - DFh
parameter[6:0] ADCON_ID = 7'b1011000;
// E0h - E7h
parameter[6:0] ACC_ID = 7'b1100000;
// E8h - EFh
parameter[6:0] MD0_ID = 7'b1101001;
parameter[6:0] MD1_ID = 7'b1101010;
parameter[6:0] MD2_ID = 7'b1101011;
parameter[6:0] MD3_ID = 7'b1101100;
parameter[6:0] MD4_ID = 7'b1101101;
parameter[6:0] MD5_ID = 7'b1101110;
parameter[6:0] ARCON_ID = 7'b1101111;
// F0h - F7h
parameter[6:0] B_ID = 7'b1110000;
parameter[6:0] EIP_ID = 7'b1110101;
// F8h - FFh
parameter[6:0] PIO_ID = 7'b1111000;
//---------------------------------------------------------------
// Special Function Register reset values
//---------------------------------------------------------------
// 80h - 87h
parameter[7:0] P0_RV = 8'b11111111;
parameter[7:0] SP_RV = 8'b00000111;
parameter[7:0] DPL_RV = 8'b00000000;
parameter[7:0] DPH_RV = 8'b00000000;
parameter[7:0] DPL1_RV = 8'b00000000;
parameter[7:0] DPH1_RV = 8'b00000000;
parameter[7:0] PCON_RV = 8'b00000000;
parameter[7:0] WDTREL_RV = 8'b00000000;
// 88h - 8Fh
parameter[7:0] TCON_RV = 8'b00000000;
parameter[7:0] TMOD_RV = 8'b00000000;
parameter[7:0] TL0_RV = 8'b00000000;
parameter[7:0] TL1_RV = 8'b00000000;
parameter[7:0] TH0_RV = 8'b00000000;
parameter[7:0] TH1_RV = 8'b00000000;
parameter[7:0] CKCON_RV = 8'b00000001;
// 90h - 97h
parameter[7:0] P1_RV = 8'b11111111;
parameter[7:0] DPS_RV = 8'b00000000;
// 98h - 9Fh
parameter[7:0] S0CON_RV = 8'b00000000;
parameter[7:0] S0BUF_RV = 8'b00000000;
parameter[7:0] IEN2_RV = 8'b00000000;
parameter[7:0] S1CON_RV = 8'b00000000;
parameter[7:0] S1BUF_RV = 8'b00000000;
parameter[7:0] S1RELL_RV = 8'b00000000;
// A0h - A7h
parameter[7:0] P2_RV = 8'b11111111;
// A8h - AFh
parameter[7:0] IEN0_RV = 8'b00000000;
parameter[7:0] IP0_RV = 8'b00000000;
parameter[7:0] IP0_RW = 8'b01000000; // Watchdog reset
parameter[7:0] S0RELL_RV = 8'b11011001;
// B0h - B7h
parameter[7:0] P3_RV = 8'b11111111;
// B8h - BFh
parameter[7:0] IEN1_RV = 8'b00000000;
parameter[7:0] IP1_RV = 8'b00000000;
parameter[7:0] S0RELH_RV = 8'b00000011;
parameter[7:0] S1RELH_RV = 8'b00000000;
// C0h - C7h
parameter[7:0] IRCON_RV = 8'b00000000;
parameter[7:0] CCEN_RV = 8'b00000000;
parameter[7:0] CCL1_RV = 8'b00000000;
parameter[7:0] CCH1_RV = 8'b00000000;
parameter[7:0] CCL2_RV = 8'b00000000;
parameter[7:0] CCH2_RV = 8'b00000000;
parameter[7:0] CCL3_RV = 8'b00000000;
parameter[7:0] CCH3_RV = 8'b00000000;
// C8h - CFh
parameter[7:0] T2CON_RV = 8'b00000000;
parameter[7:0] T2MOD_RV = 8'b00000000;
parameter[7:0] CRCL_RV = 8'b00000000;
parameter[7:0] CRCH_RV = 8'b00000000;
parameter[7:0] TL2_RV = 8'b00000000;
parameter[7:0] TH2_RV = 8'b00000000;
// D0h - D7h
parameter[7:0] PSW_RV = 8'b00000000;
// D8h - DFh
parameter[7:0] ADCON_RV = 8'b00000000;
// E0h - E7h
parameter[7:0] ACC_RV = 8'b00000000;
// E8h - EFh
parameter[7:0] MD0_RV = 8'b00000000;
parameter[7:0] MD1_RV = 8'b00000000;
parameter[7:0] MD2_RV = 8'b00000000;
parameter[7:0] MD3_RV = 8'b00000000;
parameter[7:0] MD4_RV = 8'b00000000;
parameter[7:0] MD5_RV = 8'b00000000;
parameter[7:0] ARCON_RV = 8'b00000000;
// F0h - F7h
parameter[7:0] B_RV = 8'b00000000;
parameter[7:0] EIP_RV = 8'b00000000;
// F8h - FFh
parameter[7:0] PIO_RV = 8'b00001111;
//-----------------------------------------------------------------
// Instruction Mnemonics
//-----------------------------------------------------------------
// 00H - 0Fh
parameter[7:0] NOP = 8'b00000000;
parameter[7:0] AJMP_0 = 8'b00000001;
parameter[7:0] LJMP = 8'b00000010;
parameter[7:0] RR_A = 8'b00000011;
parameter[7:0] INC_A = 8'b00000100;
parameter[7:0] INC_ADDR = 8'b00000101;
parameter[7:0] INC_IR0 = 8'b00000110;
parameter[7:0] INC_IR1 = 8'b00000111;
parameter[7:0] INC_R0 = 8'b00001000;
parameter[7:0] INC_R1 = 8'b00001001;
parameter[7:0] INC_R2 = 8'b00001010;
parameter[7:0] INC_R3 = 8'b00001011;
parameter[7:0] INC_R4 = 8'b00001100;
parameter[7:0] INC_R5 = 8'b00001101;
parameter[7:0] INC_R6 = 8'b00001110;
parameter[7:0] INC_R7 = 8'b00001111;
// 10H - 1Fh
parameter[7:0] JBC_BIT = 8'b00010000;
parameter[7:0] ACALL_0 = 8'b00010001;
parameter[7:0] LCALL = 8'b00010010;
parameter[7:0] RRC_A = 8'b00010011;
parameter[7:0] DEC_A = 8'b00010100;
parameter[7:0] DEC_ADDR = 8'b00010101;
parameter[7:0] DEC_IR0 = 8'b00010110;
parameter[7:0] DEC_IR1 = 8'b00010111;
parameter[7:0] DEC_R0 = 8'b00011000;
parameter[7:0] DEC_R1 = 8'b00011001;
parameter[7:0] DEC_R2 = 8'b00011010;
parameter[7:0] DEC_R3 = 8'b00011011;
parameter[7:0] DEC_R4 = 8'b00011100;
parameter[7:0] DEC_R5 = 8'b00011101;
parameter[7:0] DEC_R6 = 8'b00011110;
parameter[7:0] DEC_R7 = 8'b00011111;
// 20H - 2Fh
parameter[7:0] JB_BIT = 8'b00100000;
parameter[7:0] AJMP_1 = 8'b00100001;
parameter[7:0] RET = 8'b00100010;
parameter[7:0] RL_A = 8'b00100011;
parameter[7:0] ADD_N = 8'b00100100;
parameter[7:0] ADD_ADDR = 8'b00100101;
parameter[7:0] ADD_IR0 = 8'b00100110;
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