r80515.v

8051的Verilog实现

//*******************************************************************--
// Copyright (c) 1999-2003  Evatronix SA                             --
//*******************************************************************--
// Please review the terms of the license agreement before using     --
// this file. If you are not an authorized user, please destroy this --
// source code file and notify Evatronix SA immediately that you     --
// inadvertently received an unauthorized copy.                      --
//*******************************************************************--
//---------------------------------------------------------------------
// Project name         : R80515
// Project description  : R80515 Microcontroller Unit
//
// File name            : r80515.v
// File contents        : Module R80515
// Purpose              : Top-level structure of R80515
//                        Synthesisable HDL Core specifically designed
//                        for reusability.
//
// Destination library  : R80515_LIB
//
// Design Engineer      : M.B.
// Co-design Engineer   : D.L D.K. A.B. R.Z.
// Quality Engineer     : M.B.
// Version              : 1.15.V04
// Last modification    : 2002-11-26
//---------------------------------------------------------------------

`timescale 1 ns / 1 ns // timescale for following modules

//*******************************************************************--
// Modifications with respect to Version 1.01.E00 :
// 1.01.E01   :
// 1999-11-25 : Removed output rxd1o
// 1.10.E00   :
// 2001-09-03 : Implemented PMU unit
//            : Added clkpero, clkcpuo outputs
//            : Added clkper, clkcpu inputs
// 1.11.E00   :
// 2002-04-04 : Added On-Chip Debug Support Interface
// 1.13.V00   :
// 2002-09-25 : Added parameter ADDR_HIGH_P2_SEL
// 1.15.E00   :     
// 2002-10-16 : Added mamacki and memack ports 
// 1.15.E01   :     
// 2002-10-23 : Added RSTCTRL component
// 1.15.V03   :     
// 2003-01-31 : Added mempsacko port 
//*******************************************************************--

module R80515
   (
   clk,
   clkcpu,
   clkper,
   reset,
   swd,
   port0i,
   port1i,
   port2i,
   port3i,
   int0,
   int1,
   int2,
   int3,
   int4,
   int5,
   int6,
   cc0,
   cc1,
   cc2,
   cc3,
   rxd0i,
   rxd1i,
   t0,
   t1,
   t2,
   t2ex,
   debugreq,
   debugstep,
   debugprog,
   debugack,
   flush,
   fetch,
   acc,
   clkcpuo,
   clkpero,
   port0o,
   port1o,
   port2o,
   port3o,
   rxd0o,
   txd0,
   txd1,
   mempsack,
   memack,
   memdatai,
   mempsacko,
   memdatao,
   memaddr,
   mempswr,
   mempsrd,
   memwr,
   memrd,
   ramdatai,
   ramdatao,
   ramaddr,
   ramwe,
   ramoe,
   sfrdatai,
   sfrdatao,
   sfraddr,
   sfrwe,
   sfroe,  
   // my own control signal /////////////////
   eal,
   eint0,
   eint1,
   etm0,
   etm1,
   etm2,
   esrl0,
   esrl1,
   cnt0_mode,
   cnt1_mode,
   coca0_mode,
   coca1_mode,
   coca2_mode,
   coca3_mode,
   cnt2_mode,
   rtm2_mode,  
   // port inout control signal
   pio0,     
   pio1,
   pio2,
   pio3,
   // isp port control
   port_r,
   port_t,
   port_sel,
   port_o
   );

   //-----------------------------------------------------------------
   // Select high ordered half of address during indirect addressing
   //-----------------------------------------------------------------
   parameter ADDR_HIGH_P2_SEL   = 1;   
   
   //  Control signal inputs
   input    clk;           // Global clock input
   input    clkcpu;        // CPU clock input
   input    clkper;        // Peripheral clock input
   input    reset;         // Hardware reset input
   input    swd;           // Start Watchdog Timer input
   
   //  Port inputs
   input    [7:0] port0i; 
   input    [7:0] port1i; 
   input    [7:0] port2i; 
   input    [7:0] port3i; 
   
   //  External interrupt/Port alternate signals
   input    int0;          // External interrupt 0
   input    int1;          // External interrupt 1
   input    int2;          // External interrupt 2
   input    int3;          // External interrupt 3
   input    int4;          // External interrupt 4
   input    int5;          // External interrupt 5
   input    int6;          // External interrupt 6
   
   //  Compare Capture/Port alternate signals
   input    cc0;           // Compare/Capture 0 input
   input    cc1;           // Compare/Capture 1 input
   input    cc2;           // Compare/Capture 2 input
   input    cc3;           // Compare/Capture 3 input
   
   //  Serial/Port alternate signals
   input    rxd0i;         // Serial 0 receive data
   input    rxd1i;         // Serial 1 receive data
   
   //  Timer/Port alternate signals
   input    t0;            // Timer 0 external input
   input    t1;            // Timer 1 external input
   input    t2;            // Timer 2 external input
   input    t2ex;          // Timer 2 capture trigger

   // On-Chip Debug Support Interface
   input    debugreq;      // debug mode request
   input    debugstep;     // debug mode single-step
   input    debugprog;     // debugger program select

   output   debugack;      // debugger acknowledge signal
   output   flush;         // branch instruction fetch
   output   fetch;         // no-branch instruction fetch
   output   [7:0] acc;

   //  Control signal outputs
   output   clkcpuo;       // CPU clock input
   wire     clkcpuo;
   output   clkpero;       // Peripheral clock input
   wire     clkpero;
           
   //  Port outputs
   output   [7:0] port0o; 
   wire     [7:0] port0o;
   output   [7:0] port1o; 
   wire     [7:0] port1o;
   output   [7:0] port2o; 
   wire     [7:0] port2o;
   output   [7:0] port3o; 
   wire     [7:0] port3o;
   
   //  Serial/Port alternate signals
   output   rxd0o;         // Serial 0 receive clock
   wire     rxd0o;
   output   txd0;          // Serial 0 transmit data
   wire     txd0;
   output   txd1;          // Serial 1 transmit data
   wire     txd1;
   
   //  Memory interface
   input    mempsack;
   input    memack;
   input    [7:0] memdatai;
   output   mempsacko;     // Program store acknowledge
   wire     mempsacko;
   output   [7:0] memdatao; 
   output   [15:0] memaddr; 
   output   mempswr;       // Program store write enable
   output   mempsrd;       // Program store read enable
   wire     mempsrd;
   output   memwr;         // Memory write enable
   output   memrd;         // Memory read enable
   
   //  Data file interface
   input    [7:0] ramdatai; 
   output   [7:0] ramdatao; 
   wire     [7:0] ramdatao;
   output   [7:0] ramaddr; 
   wire     [7:0] ramaddr;
   output   ramwe;         // Data file write enable
   wire     ramwe;
   output   ramoe;         // Data file output enable
   wire     ramoe;  
   

   
   //  Data file interface
   input    [7:0] sfrdatai; 
   output   [7:0] sfrdatao; 
   wire     [7:0] sfrdatao;
   output   [6:0] sfraddr; 
   wire     [6:0] sfraddr;
   output   sfrwe;         // SFR write enable
   wire     sfrwe;
   output   sfroe; 
   wire     sfroe;   



   //  Read-Modify-Write Instr
   wire     rmwinstr;   
      
   
   
   // my own control signal
   output   eal;
   wire     eal;
   output   eint0;
   wire     eint0;
   output   eint1;
   wire     eint1;
   output   etm0;
   wire     etm0;
   output   etm1;
   wire     etm1;
   output   etm2;
   wire     etm2;
   output   esrl0;
   wire     esrl0;
   output   esrl1;
   wire     esrl1;
   output   cnt0_mode;
   wire     cnt0_mode;
   output   cnt1_mode;
   wire     cnt1_mode;
   output   [1:0] coca0_mode;
   output   [1:0] coca1_mode;
   output   [1:0] coca2_mode;
   output   [1:0] coca3_mode;
   wire     [1:0] coca0_mode;
   wire     [1:0] coca1_mode;
   wire     [1:0] coca2_mode;
   wire     [1:0] coca3_mode;  
   output   [1:0] cnt2_mode;
   wire     [1:0] cnt2_mode;
   output   [1:0] rtm2_mode;
   wire     [1:0] rtm2_mode;   
   
   // port inout control signal
   output   pio0;
   output   pio1;
   output   pio2;
   output   pio3; 
   wire     pio0;
   wire     pio1;
   wire     pio2;
   wire     pio3;       
   
   //  isp port control
   input    [7:0] port_t;     
   input    [1:0] port_sel;   
   input          port_o;
   
   output   [7:0] port_r;
   wire     [7:0] port_r;


   //---------------------------------------------------------------

   //---------------------------------------------------------------
   // ADC interrupt flag
   //---------------------------------------------------------------
   wire     iadc; 
   
   //---------------------------------------------------------------
   // Special function register interface
   //---------------------------------------------------------------
   wire     int_sfrwe; 
   wire     int_sfroe; 
   
   //---------------------------------------------------------------
   // Aritmetic Logic Unit
   //---------------------------------------------------------------
   wire     [7:0] accreg; 
   wire     [7:0] aluresult; 
   wire     [1:0] regsbank; 
   wire     bitvalue; 
   wire     cdjump;