📄 timer2.v
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parameter[7:0] MOV_R7_N = 8'b01111111;
// 80H - 8Fh
parameter[7:0] SJMP = 8'b10000000;
parameter[7:0] AJMP_4 = 8'b10000001;
parameter[7:0] ANL_C_BIT = 8'b10000010;
parameter[7:0] MOVC_A_PC = 8'b10000011;
parameter[7:0] DIV_AB = 8'b10000100;
parameter[7:0] MOV_ADDR_ADDR = 8'b10000101;
parameter[7:0] MOV_ADDR_IR0 = 8'b10000110;
parameter[7:0] MOV_ADDR_IR1 = 8'b10000111;
parameter[7:0] MOV_ADDR_R0 = 8'b10001000;
parameter[7:0] MOV_ADDR_R1 = 8'b10001001;
parameter[7:0] MOV_ADDR_R2 = 8'b10001010;
parameter[7:0] MOV_ADDR_R3 = 8'b10001011;
parameter[7:0] MOV_ADDR_R4 = 8'b10001100;
parameter[7:0] MOV_ADDR_R5 = 8'b10001101;
parameter[7:0] MOV_ADDR_R6 = 8'b10001110;
parameter[7:0] MOV_ADDR_R7 = 8'b10001111;
// 90H - 9Fh
parameter[7:0] MOV_DPTR_N = 8'b10010000;
parameter[7:0] ACALL_4 = 8'b10010001;
parameter[7:0] MOV_BIT_C = 8'b10010010;
parameter[7:0] MOVC_A_DPTR = 8'b10010011;
parameter[7:0] SUBB_N = 8'b10010100;
parameter[7:0] SUBB_ADDR = 8'b10010101;
parameter[7:0] SUBB_IR0 = 8'b10010110;
parameter[7:0] SUBB_IR1 = 8'b10010111;
parameter[7:0] SUBB_R0 = 8'b10011000;
parameter[7:0] SUBB_R1 = 8'b10011001;
parameter[7:0] SUBB_R2 = 8'b10011010;
parameter[7:0] SUBB_R3 = 8'b10011011;
parameter[7:0] SUBB_R4 = 8'b10011100;
parameter[7:0] SUBB_R5 = 8'b10011101;
parameter[7:0] SUBB_R6 = 8'b10011110;
parameter[7:0] SUBB_R7 = 8'b10011111;
// A0H - AFh
parameter[7:0] ORL_C_NBIT = 8'b10100000;
parameter[7:0] AJMP_5 = 8'b10100001;
parameter[7:0] MOV_C_BIT = 8'b10100010;
parameter[7:0] INC_DPTR = 8'b10100011;
parameter[7:0] MUL_AB = 8'b10100100;
parameter[7:0] UNKNOWN = 8'b10100101;
parameter[7:0] MOV_IR0_ADDR = 8'b10100110;
parameter[7:0] MOV_IR1_ADDR = 8'b10100111;
parameter[7:0] MOV_R0_ADDR = 8'b10101000;
parameter[7:0] MOV_R1_ADDR = 8'b10101001;
parameter[7:0] MOV_R2_ADDR = 8'b10101010;
parameter[7:0] MOV_R3_ADDR = 8'b10101011;
parameter[7:0] MOV_R4_ADDR = 8'b10101100;
parameter[7:0] MOV_R5_ADDR = 8'b10101101;
parameter[7:0] MOV_R6_ADDR = 8'b10101110;
parameter[7:0] MOV_R7_ADDR = 8'b10101111;
// B0H - BFh
parameter[7:0] ANL_C_NBIT = 8'b10110000;
parameter[7:0] ACALL_5 = 8'b10110001;
parameter[7:0] CPL_BIT = 8'b10110010;
parameter[7:0] CPL_C = 8'b10110011;
parameter[7:0] CJNE_A_N = 8'b10110100;
parameter[7:0] CJNE_A_ADDR = 8'b10110101;
parameter[7:0] CJNE_IR0_N = 8'b10110110;
parameter[7:0] CJNE_IR1_N = 8'b10110111;
parameter[7:0] CJNE_R0_N = 8'b10111000;
parameter[7:0] CJNE_R1_N = 8'b10111001;
parameter[7:0] CJNE_R2_N = 8'b10111010;
parameter[7:0] CJNE_R3_N = 8'b10111011;
parameter[7:0] CJNE_R4_N = 8'b10111100;
parameter[7:0] CJNE_R5_N = 8'b10111101;
parameter[7:0] CJNE_R6_N = 8'b10111110;
parameter[7:0] CJNE_R7_N = 8'b10111111;
// C0H - CFh
parameter[7:0] PUSH = 8'b11000000;
parameter[7:0] AJMP_6 = 8'b11000001;
parameter[7:0] CLR_BIT = 8'b11000010;
parameter[7:0] CLR_C = 8'b11000011;
parameter[7:0] SWAP_A = 8'b11000100;
parameter[7:0] XCH_ADDR = 8'b11000101;
parameter[7:0] XCH_IR0 = 8'b11000110;
parameter[7:0] XCH_IR1 = 8'b11000111;
parameter[7:0] XCH_R0 = 8'b11001000;
parameter[7:0] XCH_R1 = 8'b11001001;
parameter[7:0] XCH_R2 = 8'b11001010;
parameter[7:0] XCH_R3 = 8'b11001011;
parameter[7:0] XCH_R4 = 8'b11001100;
parameter[7:0] XCH_R5 = 8'b11001101;
parameter[7:0] XCH_R6 = 8'b11001110;
parameter[7:0] XCH_R7 = 8'b11001111;
// D0H - DFh
parameter[7:0] POP = 8'b11010000;
parameter[7:0] ACALL_6 = 8'b11010001;
parameter[7:0] SETB_BIT = 8'b11010010;
parameter[7:0] SETB_C = 8'b11010011;
parameter[7:0] DA_A = 8'b11010100;
parameter[7:0] DJNZ_ADDR = 8'b11010101;
parameter[7:0] XCHD_IR0 = 8'b11010110;
parameter[7:0] XCHD_IR1 = 8'b11010111;
parameter[7:0] DJNZ_R0 = 8'b11011000;
parameter[7:0] DJNZ_R1 = 8'b11011001;
parameter[7:0] DJNZ_R2 = 8'b11011010;
parameter[7:0] DJNZ_R3 = 8'b11011011;
parameter[7:0] DJNZ_R4 = 8'b11011100;
parameter[7:0] DJNZ_R5 = 8'b11011101;
parameter[7:0] DJNZ_R6 = 8'b11011110;
parameter[7:0] DJNZ_R7 = 8'b11011111;
// E0H - EFh
parameter[7:0] MOVX_A_IDPTR = 8'b11100000;
parameter[7:0] AJMP_7 = 8'b11100001;
parameter[7:0] MOVX_A_IR0 = 8'b11100010;
parameter[7:0] MOVX_A_IR1 = 8'b11100011;
parameter[7:0] CLR_A = 8'b11100100;
parameter[7:0] MOV_A_ADDR = 8'b11100101;
parameter[7:0] MOV_A_IR0 = 8'b11100110;
parameter[7:0] MOV_A_IR1 = 8'b11100111;
parameter[7:0] MOV_A_R0 = 8'b11101000;
parameter[7:0] MOV_A_R1 = 8'b11101001;
parameter[7:0] MOV_A_R2 = 8'b11101010;
parameter[7:0] MOV_A_R3 = 8'b11101011;
parameter[7:0] MOV_A_R4 = 8'b11101100;
parameter[7:0] MOV_A_R5 = 8'b11101101;
parameter[7:0] MOV_A_R6 = 8'b11101110;
parameter[7:0] MOV_A_R7 = 8'b11101111;
// F0H - FFh
parameter[7:0] MOVX_IDPTR_A = 8'b11110000;
parameter[7:0] ACALL_7 = 8'b11110001;
parameter[7:0] MOVX_IR0_A = 8'b11110010;
parameter[7:0] MOVX_IR1_A = 8'b11110011;
parameter[7:0] CPL_A = 8'b11110100;
parameter[7:0] MOV_ADDR_A = 8'b11110101;
parameter[7:0] MOV_IR0_A = 8'b11110110;
parameter[7:0] MOV_IR1_A = 8'b11110111;
parameter[7:0] MOV_R0_A = 8'b11111000;
parameter[7:0] MOV_R1_A = 8'b11111001;
parameter[7:0] MOV_R2_A = 8'b11111010;
parameter[7:0] MOV_R3_A = 8'b11111011;
parameter[7:0] MOV_R4_A = 8'b11111100;
parameter[7:0] MOV_R5_A = 8'b11111101;
parameter[7:0] MOV_R6_A = 8'b11111110;
parameter[7:0] MOV_R7_A = 8'b11111111;
//-----------------------------------------------------------------
// Interrupt reset values
//-----------------------------------------------------------------
parameter[4:0] VECT_RV = 5'b00000; // Interrupt Vector reset value
parameter[3:0] IS_REG_RV = 4'b0000; // In Service Register reset value
//-----------------------------------------------------------------
// Interrupt Vector locations
//-----------------------------------------------------------------
// external interrupt 0
parameter[4:0] VECT_E0 = 5'b00000;
// timer 0 overflow
parameter[4:0] VECT_TF0 = 5'b00001;
// external interrupt 1
parameter[4:0] VECT_E1 = 5'b00010;
// timer 1 overflow
parameter[4:0] VECT_TF1 = 5'b00011;
// serial channel 0
parameter[4:0] VECT_SER0 = 5'b00100;
// timer 2 overflow/ext. reload
parameter[4:0] VECT_TF2 = 5'b00101;
// A/D converter
parameter[4:0] VECT_ADC = 5'b01000;
// external interrupt 2
parameter[4:0] VECT_EX2 = 5'b01001;
// external interrupt 3
parameter[4:0] VECT_EX3 = 5'b01010;
// external interrupt 4
parameter[4:0] VECT_EX4 = 5'b01011;
// external interrupt 5
parameter[4:0] VECT_EX5 = 5'b01100;
// external interrupt 6
parameter[4:0] VECT_EX6 = 5'b01101;
// serial channel 1
parameter[4:0] VECT_SER1 = 5'b10000;
//-----------------------------------------------------------------
// Start address location
//-----------------------------------------------------------------
parameter[15:0] ADDR_RV = 16'b0000000000000000; //
//-----------------------------------------------------------------
// RAM & SFR address reset value
//-----------------------------------------------------------------
parameter[7:0] RAM_SFR_ADDR_RV= 8'b00000000; //
//-----------------------------------------------------------------
// Data register reset value
//-----------------------------------------------------------------
parameter[7:0] DATAREG_RV = 8'b00000000; //
//-----------------------------------------------------------------
// High ordered half of address during indirect addressing
//-----------------------------------------------------------------
parameter[7:0] ADDR_HIGH_RI = 8'b00000000; //
//-----------------------------------------------------------------
// Watchdog Timer reset value
//-----------------------------------------------------------------
parameter[6:0] WDTH_RV = 7'b0000000; // High ordered WDT
parameter[7:0] WDTL_RV = 8'b00000000; // Low ordered WDT
//-----------------------------------------------------------------
// Watchdog Timer reset state
//-----------------------------------------------------------------
parameter[14:0] WDT_RS = 15'b111111111111100; // X"7FFC"
//*******************************************************************--
// Control signals inputs
input clk; // Global clock input
input rst; // Global reset input
// Timer inputs
input t2; // Timer 2 external input
input t2ex; // Timer 2 capture trigger
// Compare Capture inputs
input cc0; // Compare/Capture 0 input
input cc1; // Compare/Capture 1 input
input cc2; // Compare/Capture 2 input
input cc3; // Compare/Capture 3 input
// Compare outputs
output com0; // Compare 0 output
wire com0;
output com1; // Compare 1 output
wire com1;
output com2; // Compare 2 output
wire com2;
output com3; // Compare 3 output
wire com3;
output [7:0] ccenreg; //ccen reg.
wire [7:0] ccenreg;
// T2CON
output i2fr;
wire i2fr;
output i3fr;
wire i3fr;
// Timer interrupt flags
output tf2; // Timer 2 overflow signal
wire tf2;
output exf2; // Timer 2 external signal
wire exf2;
// cc mode mask
output [1:0] coca0_mode; // cc0 mode mask
wire [1:0] coca0_mode;
output [1:0] coca1_mode; // cc1 mode mask
wire [1:0] coca1_mode;
output [1:0] coca2_mode; // cc2 mode mask
wire [1:0] coca2_mode;
output [1:0] coca3_mode; // cc3 mode mask
wire [1:0] coca3_mode;
// counter2 mode mask
output [1:0] cnt2_mode;
wire [1:0] cnt2_mode;
// reload of timer2 mode mask
output [1:0] rtm2_mode;
wire [1:0] rtm2_mode;
// Special function register interface
output [3:0] ccubus;
wire [3:0] ccubus;
input [7:0] sfrdatai;
output [7:0] sfrdatatim2;
wire [7:0] sfrdatatim2;
input [6:0] sfraddr;
input sfrwe;
//---------------------------------------------------------------------
// t2cm - compare mode bit -t2con(2) when 0 -mod 0
// when 1 -mod 1
// cocahl - enable compare function -ccen
// compare - signal compare in compare mode 0 directly controled port
// ov - Timer 2 Overflow in compare mode 0 directly controled port
// pout - port output
//---------------------------------------------------------------------
//---------------------------------------------------------------
// Clock counter
//---------------------------------------------------------------
reg [4:0] clk_count;
reg clk_ov12; // Clock divided by 12
reg clk_ov24; // Clock divided by 24
//---------------------------------------------------------------
// Timer 2 registers
//---------------------------------------------------------------
// Timer/Counter registers
reg [7:0] tl2;
reg [7:0] th2;
// Control registers
reg [7:0] t2con;
// Compare/capture enable register
reg [7:0] ccen;
//---------------------------------------------------------------
// Compare/Reload/Capture registers
//---------------------------------------------------------------
// Compare/Reload registers
reg [7:0] crcl;
reg [7:0] crch;
// Compare/Capture registers
reg [7:0] ccl1;
reg [7:0] cch1;
reg [7:0] ccl2;
reg [7:0] cch2;
reg [7:0] ccl3;
reg [7:0] cch3;
//---------------------------------------------------------------
// Timer 2 control signals
//---------------------------------------------------------------
// External input t2 falling edge detector
reg t2_fall; // t2 input fall edge detector
reg t2_ff0; // t2 input flip-flop
reg t2_ff; // t2 input flip-flop
// Capture input for CC register 1 rising edge detector
reg cc1_rise;
reg cc1_ff0;
reg cc1_ff;
// Capture input for CC register 2 rising edge detector
reg cc2_rise;
reg cc2_ff0;
reg cc2_ff;
// Capture input for CC register 3 rising edge detector
reg cc3_rise;
reg cc3_ff0;
reg cc3_ff;
// Capture input for CRC register falling or rising edge detector
reg cc0_fall_rise;
reg cc0_ff0;
reg cc0_ff;
// External input t2ex falling edge detector
reg t2ex_fall; // t2ex trigger fall edge detector
reg t2ex_ff0; // t2ex trigger flip-flop
reg t2ex_ff; // t2ex trigger flip-flop
// Timer 0 signals
wire t2_clk; // Timer 2 clock
wire tl2_clk; // Timer low 2 clock
wire th2_clk; // Timer high 2 clock
wire tl2_ov; // Timer low 2 overflow
wire th2_ov; // Timer high 2 overflow
// Compare signal
reg com_int0;
reg com_int1;
reg com_int2;
reg com_int3;
// Internal ports outputs
wire cc0_out_int;
wire cc1_out_int;
wire cc2_out_int;
wire cc3_out_int;
//---------------------------------------------------------------
// Compare/Capture Bit Port 0 Control
//---------------------------------------------------------------
CCU_PORT CCU_PORT_0
(
.clk (clk),
.rst (rst),
.compare (com_int0),
.ov (th2_ov),
.cocahl (ccen[1:0]),
.t2cm (t2con[2]),
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