ports.v

8051的Verilog实现

   // A/D converter 
   parameter[4:0] VECT_ADC       = 5'b01000; 
   
   // external interrupt 2
   parameter[4:0] VECT_EX2       = 5'b01001; 
   
   // external interrupt 3
   parameter[4:0] VECT_EX3       = 5'b01010; 
   
   // external interrupt 4
   parameter[4:0] VECT_EX4       = 5'b01011; 
   
   // external interrupt 5
   parameter[4:0] VECT_EX5       = 5'b01100; 
   
   // external interrupt 6
   parameter[4:0] VECT_EX6       = 5'b01101; 
   
   // serial channel 1
   parameter[4:0] VECT_SER1      = 5'b10000; 

   //-----------------------------------------------------------------
   // Start address location
   //-----------------------------------------------------------------
   parameter[15:0] ADDR_RV       = 16'b0000000000000000; //


   //-----------------------------------------------------------------
   // RAM & SFR address reset value
   //-----------------------------------------------------------------
   parameter[7:0] RAM_SFR_ADDR_RV= 8'b00000000; //


   //-----------------------------------------------------------------
   // Data register reset value
   //-----------------------------------------------------------------
   parameter[7:0] DATAREG_RV     = 8'b00000000; //


   //-----------------------------------------------------------------
   // High ordered half of address during indirect addressing
   //-----------------------------------------------------------------
   parameter[7:0] ADDR_HIGH_RI   = 8'b00000000; //


   //-----------------------------------------------------------------
   // Watchdog Timer reset value
   //-----------------------------------------------------------------
   parameter[6:0] WDTH_RV        = 7'b0000000;  // High ordered WDT
   parameter[7:0] WDTL_RV        = 8'b00000000; // Low ordered WDT


   //-----------------------------------------------------------------
   // Watchdog Timer reset state
   //-----------------------------------------------------------------
   parameter[14:0] WDT_RS        = 15'b111111111111100; // X"7FFC"



//*******************************************************************--
   
   //  Control signals inputs
   input    clk;           // Global clock input
   input    rst;           // Global reset input
   
   //  Port inputs
   input    [7:0] port0i; 
   input    [7:0] port1i; 
   input    [7:0] port2i; 
   input    [7:0] port3i; 
   
   //  CPU control signals
   input    rmwinstr;      // Read-Modify-Write Instr.
   
   //  CCU bus input
   input    [3:0] ccubus; 
   
   //  Port outputs
   output   [7:0] port0o; 
   wire     [7:0] port0o;
   output   [7:0] port1o; 
   wire     [7:0] port1o;
   output   [7:0] port2o; 
   wire     [7:0] port2o;
   output   [7:0] port3o; 
   wire     [7:0] port3o;
   
   //  Special function register interface
   input    [7:0] sfrdatai; 
   output   [7:0] sfrdataports; 
   wire     [7:0] sfrdataports;
   input    [6:0] sfraddr; 
   input    sfrwe;    
   
   
   //  Port inout control signal
   output   pio0;
   wire     pio0;
   output   pio1;
   wire     pio1;
   output   pio2;
   wire     pio2;
   output   pio3;
   wire     pio3;                                     
   
   
   //  ISP port control
   input    [7:0]  port_t;   
   input    [1:0]  port_sel;
   input           port_o; 
   input           debugreq;
   
   output   [7:0]  port_r;    
   wire     [7:0]  port_r;       
   
   wire            port_in;


   //------------------------------------------------------------------

   // Port registers
   reg      [7:0] p0; 
   reg      [7:0] p1; 
   reg      [7:0] p2; 
   reg      [7:0] p3;            
   
   
   // Port inout control SFR register
   reg      [7:0] pio;

   //------------------------------------------------------------------
   // Port 0 ouput
   //------------------------------------------------------------------
   assign port0o = p0 ; 
   
   //------------------------------------------------------------------
   // Port 1 ouput
   //------------------------------------------------------------------
   assign port1o = (debugreq == 1'b1) ? p1 : {p1[7:4], ccubus} ; 
   
   //---------------------
   // Standard solution
   // port1o = p1;
   //---------------------
   
   //------------------------------------------------------------------
   // Port 2 ouput
   //------------------------------------------------------------------
   assign port2o = p2 ; 
   
   //------------------------------------------------------------------
   // Port 3 ouput
   //------------------------------------------------------------------
   assign port3o = p3 ;      
   
   //------------------------------------------------------------------
   // Port 0 inout control signal
   //------------------------------------------------------------------                 
   assign pio0 = pio[0] ;              
                                                                       
   //------------------------------------------------------------------
   // Port 1 inout control signal
   //------------------------------------------------------------------                 
   assign pio1 = pio[1] ;                                                                         
                                                                       
   //------------------------------------------------------------------
   // Port 2 inout control signal
   //------------------------------------------------------------------                 
   assign pio2 = pio[2] ;  

   //------------------------------------------------------------------
   // Port 3 inout control signal
   //------------------------------------------------------------------                 
   assign pio3 = pio[3] ;  
   
   //------------------------------------------------------------------
   // port_in signal form isp
   //------------------------------------------------------------------    
   assign port_in = port_o ;
   
   //------------------------------------------------------------------
   // port_r databus for isp
   //------------------------------------------------------------------    
   assign port_r = (port_sel == 2'b00) ? port0o :
                   (port_sel == 2'b01) ? port1o :  
                   (port_sel == 2'b10) ? port2o :  
                   (port_sel == 2'b11) ? port3o :
                   8'h00 ;                 
                                                                          
   //------------------------------------------------------------------
   always @(posedge clk)
   begin : ports_write_proc
   //------------------------------------------------------------------
   if (rst)
      //-----------------------------------
      // Synchronous reset
      //-----------------------------------
      begin
      p0 <= P0_RV ; 
      p1 <= P1_RV ; 
      p2 <= P2_RV ; 
      p3 <= P3_RV ; 
      end
   else
      //-----------------------------------
      // Synchronous write
      //-----------------------------------
      // Special function register write
      //--------------------------------
      begin      
      if (port_in && (port_sel == 2'b00))
         begin
         p0 <= port_t;
         end
      else if (sfrwe & sfraddr == P0_ID)
         begin
         p0 <= sfrdatai ; 
         end 
         
      if (port_in && (port_sel == 2'b01))
         begin
         p1 <= port_t;
         end      
      else if (sfrwe & sfraddr == P1_ID)
         begin
         p1 <= sfrdatai ; 
         end 
         
      if (port_in && (port_sel == 2'b10))
         begin
         p2 <= port_t;
         end      
      else if (sfrwe & sfraddr == P2_ID)
         begin
         p2 <= sfrdatai ; 
         end 
      
      if (port_in && (port_sel == 2'b11))
         begin
         p3 <= port_t;
         end      
      else if (sfrwe & sfraddr == P3_ID)
         begin
         p3 <= sfrdatai ; 
         end       
      end  
   end 
   
   //------------------------------------------------------------------
   // Special Function registers read
   //------------------------------------------------------------------
   assign sfrdataports =
      (sfraddr == P0_ID & rmwinstr) ? p0 :
      (sfraddr == P1_ID & rmwinstr) ? p1 :
      (sfraddr == P2_ID & rmwinstr) ? p2 :
      (sfraddr == P3_ID & rmwinstr) ? p3 :
      (sfraddr == P0_ID & !rmwinstr) ? port0i :
      (sfraddr == P1_ID & !rmwinstr) ? port1i :
      (sfraddr == P2_ID & !rmwinstr) ? port2i :
      (sfraddr == P3_ID & !rmwinstr) ? port3i :
      "--------" ;        
      
      
      
    // Port inout control signal SFR register
    
    always @ (posedge clk)
      begin
        if (rst)
          begin
            pio <= PIO_RV ;
          end
        else 
          if (sfrwe & sfraddr == PIO_ID)  
            begin
              pio <= sfrdatai ;
            end
      end


endmodule  //  module PORTS

//*******************************************************************--