rstctrl.v

8051的Verilog实现

//*******************************************************************--
// Copyright (c) 1999-2003  Evatronix SA                             --
//*******************************************************************--
// Please review the terms of the license agreement before using     --
// this file. If you are not an authorized user, please destroy this --
// source code file and notify Evatronix SA immediately that you     --
// inadvertently received an unauthorized copy.                      --
//*******************************************************************--
//---------------------------------------------------------------------
// Project name         : R80515
// Project description  : R80515 Microcontroller Unit
//
// File name            : rstctrl.v
// File contents        : Module RSTCTRL
// Purpose              : 
//
// Destination library  : R80515_LIB
//
// Design Engineer      : D.K. A.B.
// Quality Engineer     : M.B.
// Version              : 1.15.V04
// Last modification    : 2003-04-15
//---------------------------------------------------------------------

`timescale 1 ns / 1 ns // timescale for following modules

//*******************************************************************--
// Modifications with respect to Version 1.15.E01 :
// 1.15.E01   :
// 2002-10-23 : The RSRCTRL is added to this version
//*******************************************************************--

module RSTCTRL
  (
  clk,
  rst,
  reset,
  wdts,
  intreq,
  int0,
  int1,
  it0,
  it1,
  isreg,
  intprior0,
  intprior1,
  eal,
  eint0,
  eint1,
  mempsrdrst,
  pmuintreq
  );

  // Control signals inputs
  input     clk;          // Global clock input
  input     rst;          // Internal reset input
  input     reset;        // Hardware reset input

  // Watchdog Timer reset request
  input     wdts;         // WDT status flag

  // Interrupt requests
  input     intreq;       // from ISR
  input     int0;         // external interrupt 0
  input     int1;         // external interrupt 1

  // External interrupt type select
  input     it0;          // interrupt 0 type select
  input     it1;          // interrupt 1 type select

  // In service register
  input     [3:0] isreg; 

  // Interrupt Priority registers
  input     [1:0] intprior0; 
  input     [1:0] intprior1;

  // Interrupt mask 
  input     eal;          // Enable all interrupts 
  input     eint0;        // external interrupt 0 mask
  input     eint1;        // external interrupt 1 mask


  output    mempsrdrst;   // memory read signal reset
  wire      mempsrdrst;
  output    pmuintreq; 
  wire      pmuintreq;

//*******************************************************************--

  wire      int_req_c;    // Interrupt request comb.
  reg       int_req;      // Interrupt request sync.e
  reg       reset_ff;     // external reset flip-flop
  reg       rst_o;        // internal reset flip-flop 

  // Watchdog Timer reset detector
  reg       wdts_ff; 

  //------------------------------------------------------------------
  // Program memory read signal reset
  //------------------------------------------------------------------
  assign mempsrdrst = rst_o ; 

  //------------------------------------------------------------------
  // Interrupt request to PMU 
  //------------------------------------------------------------------
  assign pmuintreq = int_req ; 

  //------------------------------------------------------------------
  // Combinational interrupt request
  // Low active 
  //------------------------------------------------------------------
  assign int_req_c =
         (
          (intreq) |                                   // ISR intreq
          (eal & 
           (
            (!int0 & eint0 & !it0 &                    // ext. int. 0
             (
              ( (intprior0[0]) &  (intprior1[0]) & !(isreg[3])) | // l3
              (!(intprior0[0]) &  (intprior1[0]) & !(isreg[3]) &  // l2
               !(isreg[2])) |
              ( (intprior0[0]) & !(intprior1[0]) & !(isreg[3]) &  // l1
               !(isreg[2]) & !(isreg[1])) |
              (!(intprior0[0]) & !(intprior1[0]) & !(isreg[3]) &  // l0
               !(isreg[2]) & !(isreg[1]) & !(isreg[0]))
             )
            ) |
            (!int1 & eint1 & !it1 &                    // ext. int. 1
             (
              ( (intprior0[1]) &  (intprior1[1]) & !(isreg[3])) | // l3
              (!(intprior0[1]) &  (intprior1[1]) & !(isreg[3]) &  // l2
               !(isreg[2])) |
              ( (intprior0[1]) & !(intprior1[1]) & !(isreg[3]) &  // l1
               !(isreg[2]) & !(isreg[1])) |
              (!(intprior0[1]) & !(intprior1[1]) & !(isreg[3]) &  // l0
               !(isreg[2]) & !(isreg[1]) & !(isreg[0]))
             )
            )
           )
          )
         ) ? 1'b1 : 1'b0 ; 

  //------------------------------------------------------------------
  // Interrupt request
  // Synchronous section 
  //------------------------------------------------------------------
  always @(posedge clk)
  begin : int_req_write_proc
  //------------------------------------------------------------------   
  //-----------------------------------
  // Synchronous reset
  //-----------------------------------
  if (rst)
    begin
    int_req <= 1'b0 ; 
    end
  else
    begin
    //-----------------------------------
    // Synchronous write
    //-----------------------------------
    int_req <= int_req_c ; 
    end  
  end 

  //------------------------------------------------------------------
  // Internal synchronous reset generator
  //------------------------------------------------------------------
  always @(posedge clk)
  begin : reset_gen_proc
  //------------------------------------------------------------------   
  //-----------------------------------
  // Synchronous write
  //-----------------------------------
  // internal reset flip-flop
  //-----------------------------------
  if ((reset & reset_ff) | (wdts & !wdts_ff))
    begin
    rst_o <= 1'b1 ; 
    end
  else
    begin
    rst_o <= 1'b0 ; 
    end 
  //-----------------------------------
  // reset input flip-flop
  //-----------------------------------
  reset_ff <= reset ;  
  end 

  //------------------------------------------------------------------
  // Watchdog timer status flag flip-flop
  //------------------------------------------------------------------
  always @(posedge clk)
  begin : wdts_ff_write_proc
  //------------------------------------------------------------------
  //-----------------------------------
  // Synchronous reset
  //-----------------------------------
  if (rst)
    begin
    wdts_ff <= 1'b0 ; 
    end
  else
    begin
    //-----------------------------------
    // Synchronous write
    //-----------------------------------
    wdts_ff <= wdts ; 
    end  
  end 

endmodule // module RSTCTRL

//*******************************************************************--