kt.v
来自「sha加密算法实现」· Verilog 代码 · 共 65 行
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65 行
////////////////////////////////////////////////////////////////////////// //// Abstract : SHA-1 Kt module //// //// Module : kt //// //// Version : ver 01.00 //// //// Modification History : //// Date By Change Description //// ----------------------------------------------------------------- //// 2008/02/26 hwj Initial //// YYYY/MM/DD author Revision content //// ////////////////////////////////////////////////////////////////////////////Constant for each round`define SHA1_K1 32'h5a827999`define SHA1_K2 32'h6ed9eba1`define SHA1_K3 32'h8f1bbcdc`define SHA1_K4 32'hca62c1d6module kt( clk_i, rst_n, round_con, kt_o);//--------------------------------------------------------------------//// IO define ////--------------------------------------------------------------------// input clk_i; // global clock inputinput rst_n; // global reset input , active highinput [7:0] round_con;output [31:0] kt_o;//--------------------------------------------------------------------// // Local Registers and wires ////--------------------------------------------------------------------// wire [7:0] round_con;reg [31:0] kt_o;parameter DELAY = 1; //--------------------------------------------------------------------// // KT assignment ////--------------------------------------------------------------------// always @ (posedge clk_i)begin if(~rst_n) kt_o <= #DELAY 'b0; else begin if (round_con < 8'd20) kt_o <= #DELAY `SHA1_K1; else if (round_con < 8'd40) kt_o <= #DELAY `SHA1_K2; else if (round_con < 8'd60) kt_o <= #DELAY `SHA1_K3; else kt_o <= #DELAY `SHA1_K4; endendendmodule
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