wt_8bit.v

sha加密算法实现

////////////////////////////////////////////////////////////////////////
//                                                                    //
//  Abstract             : SHA-1 Wt module                            //
//                                                                    //
//  Module               : wt                                         //
//                                                                    //
//  Version              : ver 01.00                                  //
//                                                                    //
//  Modification History :                                            //
//  Date        By         Change Description                         //
//  ----------------------------------------------------------------- //
//  2008/02/26  hwj        Initial                                    //
//  2008/03/06  hwj        revise for 8-bit bus interface             //
//                                                                    //
////////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps

module wt(clk_i,
          rst_n,
          en, 
          data_i,
          round_con,
          mem_con,
          wt_con,
          wt_o );
//--------------------------------------------------------------------//
//                         IO define                                  //
//--------------------------------------------------------------------//
input            clk_i;
input            rst_n;
input            en;
input   [7:0]    round_con;
input   [31:0]   data_i;
input   [1:0]    mem_con;

output  [2:0]    wt_con;
output  [31:0]   wt_o;
//--------------------------------------------------------------------// 
//                   Local Registers and wires                        //
//--------------------------------------------------------------------//
reg     [31:0]   wt_o;    //output register
reg     [31:0]   wt_t;    //temp register for wt

reg     [2:0]    wt_con;  //count for wt

reg              xor_en;  //mux control signal for xor
reg              rotl_en; //mux control signal for shift 1 bit

//--------------------------------------------------------------------// 
//                           Controller                               //
//--------------------------------------------------------------------//

//-------------
// wt counter
//-------------
//count from 0 to 4
always @(posedge clk_i)
begin
  if(~rst_n)
    wt_con <= 3'b000;
  else
    if(en)
      if(wt_con != 3'b101)
        if(mem_con == 2'b11)
          wt_con <= wt_con + 1'b1;
        else
          wt_con <= wt_con;
      else
        if((round_con != 8'd80) && (mem_con == 2'b11))
          wt_con <= 3'b001;
        else
          if((round_con == 8'd80) && (mem_con == 2'b11))
            wt_con <= 3'b000; //clear for the next sha computing
          else
            wt_con <= wt_con;
    else
      wt_con <= 3'b000;
end

//-------------
// wt control
//-------------
always @(posedge clk_i)
begin
  if(~rst_n)
    xor_en <= 1'b1;
  else
    if((wt_con[2:1]!=2'b00) && (mem_con == 2'b00))  //one round wt compute finish
      xor_en <= 1'b1;
    else
      xor_en <= 1'b0;
end

always @(posedge clk_i)
begin
  if(~rst_n)
    rotl_en <= 1'b0;
  else
    //if(wt_con == 3'b100 )   //final step: shift wt_t 1 bit
    if((wt_con == 3'b101)&&(mem_con == 2'b10))
      rotl_en <= 1'b1;
    else
      rotl_en <= 1'b0;
end

//--------------------------------------------------------------------//
//                           Data Path                                //
//--------------------------------------------------------------------//
always @(posedge clk_i)
begin
  if(~rst_n)
    wt_t <= 32'd0;
  else
    if(wt_con != 3'b001)
      if(xor_en)
        wt_t <= wt_t ^ data_i;         //xor
      else
        wt_t <= wt_t;
    else
      if(mem_con == 2'b01)
        wt_t <= 32'd0;
end

always @(rotl_en or wt_t or round_con or data_i)
begin
    if(round_con < 8'd16)
      wt_o = data_i;
    else
      if(rotl_en)
        wt_o = {wt_t[30:0],wt_t[31]};  //rotl
      else
        wt_o = wt_t;
end
endmodule