📄 sha_top.v
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//------------------------
// A B C D E compute path
//------------------------
assign b_rotl30 = {b_r[1:0],b_r[31:2]};
always @(posedge clk_i)
begin
if(~rst_n)
a_r <= 32'h67452301;
else
if(en)
if(((wt_con == 3'b101) && (mem_con == 2'b11))
|| ((round_con == 8'd80)&& (mem_con == 2'b11)))
a_r <= add_o;
else
a_r <= a_r;
else
a_r <= 32'h67452301;
end
always @(posedge clk_i)
begin
if(~rst_n)
b_r <= 32'hefcdab89;
else
if(en)
if(((wt_con == 3'b101) && (mem_con == 2'b11))
|| ((round_con == 8'd80)&& (mem_con == 2'b11)))
b_r <= a_r;
else
b_r <= b_r;
else
b_r <= 32'hefcdab89;
end
always @(posedge clk_i)
begin
if(~rst_n)
c_r <= 32'h98badcfe;
else
if(en)
if((wt_con == 3'b101) && (mem_con == 2'b11))
if(mux_c)
c_r <= b_rotl30;
else
c_r <= b_r;
else
if((round_con == 8'd80)&& (mem_con == 2'b11))
c_r <= b_r;
else
c_r <= c_r;
else
c_r <= 32'h98badcfe;
end
always @(posedge clk_i)
begin
if(~rst_n)
d_r <= 32'h10325476;
else
if(en)
if(((wt_con == 3'b101) && (mem_con == 2'b11))
|| ((round_con == 8'd80)&& (mem_con == 2'b11)))
d_r <= c_r;
else
d_r <= d_r;
else
d_r <= 32'h10325476;
end
always @(posedge clk_i)
begin
if(~rst_n)
e_r <= 32'hc3d2e1f0;
else
if(en)
if((wt_con[2:1] == 2'b00) && (round_con != 8'd80))
e_r <= e_r;
else
if((round_con == 8'd80)&& (mem_con == 2'b11))
e_r <= d_r;
else
if((mux_e == 1'b1) && (mem_con == 2'b11))
e_r <= add_o;
else
if((mux_e == 1'b0) && (mem_con == 2'b11))
e_r <= d_r;
else
e_r <= e_r;
else
e_r <= 32'hc3d2e1f0;
end
//--------------------------------------------------------------------//
// SHA interface //
//--------------------------------------------------------------------//
//--------------------
//interface control
//--------------------
//--------------------------------
// 8-bit interface block counter
//--------------------------------
//count from 0 to 4
always @(posedge clk_i)
begin
if(~rst_n)
mem_con <= 2'b00;
else
if(en)
if(mem_con != 2'b11)
mem_con <= mem_con + 1'b1;
else
mem_con <= 2'b00;
else
mem_con <= 2'b00;
end
//read data from register file
always @(posedge clk_i)
begin
if(~rst_n)
reg_read <= 1'b1;
else
if(en)
if(round_con < 8'd16)
reg_read <= 1'b1;
else
if(round_con != 8'd80)
if((wt_con == 3'b100)&&(mem_con==2'b11))
reg_read <= 1'b0;
else
if((wt_con == 3'b101)&&(mem_con==2'b11))
reg_read <= 1'b1;
else
reg_read <= reg_read;
else
//if((wt_con==3'd0)&&(mem_con==2'd0))
if(done)
reg_read <= 1'b1; //it is write time
else
reg_read <= 1'b0;
else
reg_read <= 1'b1; //return to the initial value
end
//write data to register file
always @(posedge clk_i)
begin
if(~rst_n)
reg_write <= 1'b0;
else
if(en)
if(round_con < 8'd17) //delay to write
reg_write <= 1'b0;
else
if(round_con != 8'd80)
if((wt_con == 3'b100)&&(mem_con== 2'b11))
reg_write <= 1'b1;
else
if((wt_con == 3'b101)&&(mem_con== 2'b11))
reg_write <= 1'b0;
else
reg_write <= reg_write;
else
//if((wt_con==3'd0)&&(mem_con==2'd0))
if(done)
reg_write <= 1'b0;
else
reg_write <= 1'b1; //it is write time
else
reg_write <= 1'b0; //return to the initial value
end
//address control
always @(posedge clk_i)
begin
if(~rst_n)
reg_addr_r_base <= 8'd0;
else
if(en)
if((round_con < 8'd15)
||((round_con == 8'd15)&&(wt_con[2]!=1'b1)))
begin
reg_addr_r_base <= round_con[3:0]; // read data for first 16 round
end
else
if(round_con != 8'd80)
begin //: wt operation
case({mem_con,wt_con}) //read from the register file
{2'b11,3'b101} : reg_addr_r_base <= round_con - 8'd15 ;
{2'b11,3'b001} : reg_addr_r_base <= round_con - 8'd14 ;
{2'b11,3'b010} : reg_addr_r_base <= round_con - 8'd8 ;
{2'b11,3'b011} : reg_addr_r_base <= round_con - 8'd3 ;
default : ;
endcase
end
else
reg_addr_r_base <= 8'd0;
else
reg_addr_r_base <= 8'd0;
end
always @(posedge clk_i)
begin
if(~rst_n)
reg_addr_w_base <= 8'd0;
else
if(round_con > 8'd15)
if(round_con == 8'd80)
begin
case(wt_con)
3'b001 : reg_addr_w_base <= 8'd1 ; //write new hash value
3'b010 : reg_addr_w_base <= 8'd2 ;
3'b011 : reg_addr_w_base <= 8'd3 ;
3'b100 : reg_addr_w_base <= 8'd4 ;
3'b101 : reg_addr_w_base <= 8'd5 ;
default : ;
endcase
end
else
if((wt_con == 3'b101)&&(mem_con == 2'b11))
reg_addr_w_base <= round_con; //write new wt
end
always @(posedge clk_i)
begin
if(~rst_n)
mem_con_d <= 2'b00;
else
mem_con_d <= mem_con;
end
assign reg_addr_w = (round_con != 8'd80) ? {reg_addr_w_base[3:0],mem_con} :
{reg_addr_w_base[3:0],mem_con_d} ;
assign reg_addr_r = {reg_addr_r_base[3:0],mem_con} ;
assign sha_addr = (reg_read == 1'b1) ? {2'b00, reg_addr_r} : (reg_write == 1'b1) ?
{2'b00,reg_addr_w} : 8'd0;
assign rst_n = ~rst;
//------------------------
// Data convert
//------------------------
// convert 8 bit * 4 -> 32 bit
// read buffer
always @(posedge clk_i)
begin
if(~rst_n)
read_buf <= 32'd0;
else
if(en)
begin
case(mem_con)
2'b01 : read_buf[31:24] <= reg_data_i ;
2'b10 : read_buf[23:16] <= reg_data_i ;
2'b11 : read_buf[15:8] <= reg_data_i ;
2'b00 : read_buf[7:0] <= reg_data_i ;
endcase
end
end
// write buffer
always @(posedge clk_i)
begin
if(~rst_n)
reg_data_o <= 8'd0;
else
if(en)
begin
if(round_con != 8'd80)
case(mem_con)
2'b11 : reg_data_o <= write_buf[31:24] ;
2'b00 : reg_data_o <= write_buf[23:16] ;
2'b01 : reg_data_o <= write_buf[15:8] ;
2'b10 : reg_data_o <= write_buf[7:0] ;
endcase
else
case(mem_con_d)
2'b11 : reg_data_o <= add_o[31:24] ;
2'b00 : reg_data_o <= write_buf[23:16] ;
2'b01 : reg_data_o <= write_buf[15:8] ;
2'b10 : reg_data_o <= write_buf[7:0] ;
endcase
end
else
reg_data_o <= 8'd0;
end
//-----------------------
// Data input/output
//-----------------------
//input
assign wt_in = read_buf;
//output
always @(posedge clk_i)
begin
if(~rst_n)
write_buf <= 32'd0;
else
if(en)
if(round_con > 8'd15)
if(round_con == 8'd80) //? need debug
write_buf <= add_o;
else
if((wt_con == 3'b101)&&(mem_con == 2'b11))
write_buf <= wt_w;
end
endmodule
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