sha_top.v

sha加密算法实现

////////////////////////////////////////////////////////////////////////
//                                                                    //
//  Abstract             : SHA-1 top level module                     //
//                                                                    //
//  Module               : sha_top                                    //
//                                                                    //
//  Version              : ver 01.00                                  //
//                                                                    //
//  Modification History :                                            //
//  Date        By         Change Description                         //
//  ----------------------------------------------------------------- //
//  2008/02/25  hwj        Initial                                    //
//  2008/03/06  hwj        revise for 8-bit bus interface             //
//                                                                    //
////////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps

module sha_top(clk_i,
               rst,
               en,
               reg_data_i,               
               reg_write,
               reg_read,
               sha_addr,
               reg_data_o,
               done,
               round_con
               );
//--------------------------------------------------------------------//
//                         IO define                                  //
//--------------------------------------------------------------------//
input           clk_i;       //input clock
input           rst;       //low active, asynchronous
input           en;
input  [7:0]    reg_data_i;

output          reg_write;
output          reg_read;
output [7:0]    sha_addr;
output [7:0]    reg_data_o;
output          done;
output [7:0]    round_con;
//--------------------------------------------------------------------// 
//                   Local Registers and wires                        //
//--------------------------------------------------------------------//

//-------------------
// output register
//-------------------
reg             reg_write;
reg             reg_read;
reg [7:0]    	reg_data_o;
reg             done;
//-------------------
// output wire
//-------------------
wire           rst_n;
wire [7:0]     sha_addr;  

wire [5:0]     reg_addr_r;
wire [5:0]     reg_addr_w;   
   
//-------------------
//wt module signals
//------------------- 
wire   [31:0]   wt_w;       //wt output register
wire   [31:0]   wt_in;      //wt input register
wire   [2:0]    wt_con;     //wt counter output

//-------------------
//data control logic
//-------------------
reg    [7:0]    round_con;  //counter for rounds
reg             mux_add;
reg    [1:0]    sel_func;   //select add op
reg             mux_c;
reg             mux_e;

//-------------------
//data path registers
//-------------------
reg    [31:0]   a_r;
reg    [31:0]   b_r;
reg    [31:0]   c_r;
reg    [31:0]   d_r;
reg    [31:0]   e_r;

reg    [31:0]   h0;
reg    [31:0]   h1;
reg    [31:0]   h2;
reg    [31:0]   h3;
reg    [31:0]   h4;

//--------------------
//intermedia signals
//--------------------
reg    [31:0]   add_o;
wire   [31:0]   add_op;
reg    [31:0]   op_func;

wire   [31:0]   ft;
wire   [31:0]   ft1;
wire   [31:0]   ft2;
wire   [31:0]   ft3;

wire   [31:0]   a_rotl5;
wire   [31:0]   b_rotl30;
wire   [31:0]   kt_o;

//--------------------------
// interface control signal
//--------------------------
reg    [1:0]    mem_con;
reg    [1:0]    mem_con_d;
reg    [5:0]    reg_addr_r_base; //base adddress of read
reg    [5:0]    reg_addr_w_base; // base address of write
reg    [31:0]   read_buf;        // read buffer
reg    [31:0]   write_buf;       // write buffer
//--------------------------------------------------------------------// 
//                           Instantiation                            //
//--------------------------------------------------------------------//

//----------
//kt module 
//----------
kt     KT_m(  .clk_i(clk_i),
              .rst_n(rst_n),
              .round_con(round_con),
              .kt_o(kt_o));

//-----------
//wt module
//-----------
wt     WT_m(  .clk_i(clk_i),
              .rst_n(rst_n),
              .en(en), 
              .data_i(wt_in),
              .round_con(round_con),
              .mem_con(mem_con),
              .wt_con(wt_con),
              .wt_o(wt_w) );

//--------------------------------------------------------------------// 
//                           Controller                               //
//--------------------------------------------------------------------//

//-------------
//step counter
//-------------
//count from 0 to 79
always @(posedge clk_i)
begin
  if(~rst_n)
    round_con <= 8'd0;
  else
    if(en)
      if(round_con != 8'd80)
        if((wt_con==3'b101)&&(mem_con == 2'b11))  //wt is ready
          round_con <= round_con + 1'b1;
        else
          round_con <= round_con;
      else
        //if((wt_con==3'b101)&&(mem_con == 2'b11))
        //  round_con <= 8'd0;
        //else
          round_con <= round_con;
    else
      round_con <= 8'd0;
end


//-----------------------
//data operation control
//-----------------------
always @(posedge clk_i)
begin
  if(~rst_n)
    mux_add <= 1'b1;
  else
    if((round_con == 8'd79) && (wt_con == 3'b101) && (mem_con==2'b11))
      mux_add <= 1'b0;
    else
      if((round_con == 8'd80) && (wt_con == 3'b101)&& (mem_con==2'b11))
      mux_add <= 1'b1;
end

always @(wt_con)
begin
  case(wt_con)
  3'b000  : sel_func <= 2'b00;
  3'b001  : sel_func <= 2'b00;
  3'b010  : sel_func <= 2'b00;
  3'b011  : sel_func <= 2'b01;
  3'b100  : sel_func <= 2'b10;
  3'b101  : sel_func <= 2'b11;
  default : sel_func <= 2'b00;
endcase
end

always @(posedge clk_i)
begin
  if(~rst_n)
    mux_c <= 1'b0;
  else
    if((round_con == 8'd0) && (wt_con == 3'b100))
      mux_c <= 1'b1;
    else
      if((round_con == 8'd79) && (wt_con == 3'b101)&&(mem_con == 2'b11))
        mux_c <= 1'b0; 
end

always @(posedge clk_i)
begin
  if(~rst_n)
    mux_e <= 1'b1;
  else
    if((wt_con == 3'b100)&&(mem_con == 2'b11))
      mux_e <= 1'b0;
    else
     if((wt_con == 3'b101)&&(mem_con == 2'b11))
       mux_e <= 1'b1;
end


// Output flag signal
always @(posedge clk_i)
begin
  if(~rst_n)
    done <= 1'b0;
  else
    if((wt_con == 3'b101) && (round_con == 8'd80)&&(mem_con == 2'b11)) //last round
      done <= 1'b1;
    else
      done <= 1'b0;
end
//--------------------------------------------------------------------//
//                           Data Path                                //
//--------------------------------------------------------------------//

//---------------------
//temp Hash reigisters
//---------------------
always @(posedge clk_i)
begin
  if(~rst_n)
    begin
      h0 <= 32'h67452301;
      h1 <= 32'hefcdab89;
      h2 <= 32'h98badcfe;
      h3 <= 32'h10325476;
      h4 <= 32'hc3d2e1f0;
    end
  else
    if((round_con == 8'd80) && (en == 1'b1))
      if(mem_con == 2'b11)
        begin
          h0 <= add_o;
          h1 <= h0;
          h2 <= h1;
          h3 <= h2;
          h4 <= h3;
        end
      else
        begin
          h0 <= h0;
          h1 <= h1;
          h2 <= h2;
          h3 <= h3;
          h4 <= h4;
        end
    else
      if(en == 1'b0)
        begin
         h0 <= 32'h67452301;
         h1 <= 32'hefcdab89;
         h2 <= 32'h98badcfe;
         h3 <= 32'h10325476;
         h4 <= 32'hc3d2e1f0;
        end
end
//---------------------
// compute a new e  
//---------------------
//left shift a for 5 bits
assign a_rotl5 = {a_r[26:0],a_r[31:27]};

// ft function select
assign ft1 = (b_r & c_r) ^ (~b_r & d_r);
assign ft2 = b_r ^ c_r ^ d_r;
assign ft3 = (b_r & c_r) ^ (c_r & d_r) ^ (b_r & d_r);
	
assign ft =   (round_con < 8'd20) ? ft1 
            : (round_con < 8'd40) ? ft2 
            : (round_con < 8'd60) ? ft3 
            :  ft2;	

//function select for adder
always @(ft or kt_o or a_rotl5 or wt_w or sel_func)
begin
  case(sel_func)
    2'b00 :  op_func = ft;
    2'b01 :  op_func = a_rotl5;
    2'b10 :  op_func = kt_o;
    2'b11 :  op_func = wt_w;
  endcase
end

//op select for adder
assign add_op = (mux_add == 1'b1) ? op_func : h4 ;

//32 bits adder
always @(e_r or add_op)
begin
  add_o = e_r + add_op;
end