des3_top.v

3des加密算法实现

////////////////////////////////////////////////////////////////////////
//                                                                    
//  Abstract: This function of the top module mostly deals with interface of the datain and dataout.                                                      
//            Change 8 bit data into 64 data.
//            Address 8h'00-8h'17 is key,8h'18-8h'1f is data. 
//                                                             
//  Module  : top_3des                                
//                                                                    
//  Version : ver 01.00                                  
//                                                                    
//  Modification History:                                            
//  Date By         Change Description                         
//  ----------------------------------------------------------------- 
//  2008/08/06  jackie                                           
//  YYYY/MM/DD  author     Revision content                           
//                                                                    
////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
module des3_top(des_datao,des_addr,des_oe,des_we,des_done,des_datai,des_en,des3,des_decode,clk,rst,
                 load_1,load_2,load_3,done_1,done_2,done_3);
output  [7:0]   des_datao;
output  [7:0]   des_addr;
output          des_oe;
output          des_we;
output          des_done;
input   [7:0]   des_datai;
input           des_en;
input           des3;
input           des_decode;
input           clk;
input           rst;
output          load_1;
output          load_2;
output          load_3;
output          done_1;
output          done_2;
output          done_3;


reg	[7:0]	key10, key11, key12, key13, key14, key15, key16, key17;
reg	[7:0]	key20, key21, key22, key23, key24, key25, key26, key27;
reg	[7:0]	key30, key31, key32, key33, key34, key35, key36, key37;
reg     [7:0]   datain_00,datain_01,datain_02,datain_03,datain_04,datain_05,datain_06,datain_07;
reg     [7:0]   in_cnt;
reg     [7:0]   out_cnt;
reg             des_en_delay1;
reg             des_en_delay2;
reg             done_temp1;
reg             done_temp2;
reg     [7:0]   des_addr_r;
reg     [7:0]   des_addr_w;
reg             en;
reg     [7:0]   des_datao;
reg             des_done;


wire    [7:0]     dataout_00,dataout_01,dataout_02,dataout_03,dataout_04,dataout_05,dataout_06,dataout_07; 
wire    [55:0]    key1;
wire    [55:0]    key2;
wire    [55:0]    key3;
wire    [63:0]    datain;
wire    [63:0]    dataout;
wire    [63:0]    cipdataout;
wire    [63:0]    invdataout;
wire              done;
wire              invdone;
wire              cipdone;
wire              des3_sta;
wire              cipen;
wire              inven;  
wire              load_1;
wire              load_2;
wire              load_3;
wire              done_1;
wire              done_2;
wire              done_3;


parameter delay = 1'b1;
parameter Low = 1'b0;

always @(posedge clk)
  if (rst)
      des_en_delay1 <= #delay 1'b0;
  else 
      des_en_delay1 <= #delay des_en;

always @(posedge clk)
  if (rst)
      des_en_delay2 <= #delay 1'b0;
  else 
      des_en_delay2 <= #delay des_en_delay1;

assign des_oe = des_en&&(!en); 

assign des_we = done_temp1&&done_temp2;

always @(posedge clk)
   if (rst)
      done_temp1 <= #delay 1'b0;
   else if (done)
      done_temp1 <= #delay 1'b1;
   else if (!des_en)
      done_temp1 <= #delay 1'b0; 
      
always @(posedge clk)
   if (rst)
      done_temp2 <= #delay 1'b0;
    else
      done_temp2 <= #delay done_temp1;       

always @(posedge clk)
   if (rst)
      en <= #delay 1'b0;    
   else if (in_cnt==8'h1f)  
      en <= #delay des_en_delay2;
   

//des_done
always @(posedge clk)
  if (rst) 
      des_done <= #delay 1'b0;
  else if (out_cnt==8'h1e)
      des_done <= #delay 1'b1;
  else 
      des_done <= #delay 1'b0;
          
assign des3_sta = des_en&&(!des_en_delay1);

always @(posedge clk)
   if (rst)
      in_cnt <= #delay 8'h00;    
   else if (des3_sta)  
      in_cnt <= #delay in_cnt-1;
   else if (des_en_delay2)  
      in_cnt <= #delay in_cnt+1;
   else
      in_cnt <= #delay 8'h00;     

//data out count
always @(posedge clk)
   if (rst)
      out_cnt <= #delay 8'h18;
   else if (done_temp1)  
      out_cnt <= #delay out_cnt+1;
   else 
      out_cnt <= #delay 8'h18;

always @(posedge clk)
   if (rst)
     begin 
        key10 <= #delay 8'h00;
        key11 <= #delay 8'h00;
        key12 <= #delay 8'h00;
        key13 <= #delay 8'h00;
        key14 <= #delay 8'h00;
        key15 <= #delay 8'h00;
        key16 <= #delay 8'h00;
        key17 <= #delay 8'h00;
        key20 <= #delay 8'h00;
        key21 <= #delay 8'h00;
        key22 <= #delay 8'h00;
        key23 <= #delay 8'h00;
        key24 <= #delay 8'h00;
        key25 <= #delay 8'h00;
        key26 <= #delay 8'h00;
        key27 <= #delay 8'h00;
        key30 <= #delay 8'h00;
        key31 <= #delay 8'h00;
        key32 <= #delay 8'h00;
        key33 <= #delay 8'h00;
        key34 <= #delay 8'h00;
        key35 <= #delay 8'h00;
        key36 <= #delay 8'h00;
        key37 <= #delay 8'h00;
        datain_00 <= #delay 8'h00;
        datain_01 <= #delay 8'h00;
        datain_02 <= #delay 8'h00;
        datain_03 <= #delay 8'h00;
        datain_04 <= #delay 8'h00;  
        datain_05 <= #delay 8'h00;  
        datain_06 <= #delay 8'h00;  
        datain_07 <= #delay 8'h00;        
     end  
   else if(des_en_delay2)
     case(in_cnt)      
      8'h00:  key10 <= #delay des_datai;
      8'h01:  key11 <= #delay des_datai;
      8'h02:  key12 <= #delay des_datai;
      8'h03:  key13 <= #delay des_datai;
      8'h04:  key14 <= #delay des_datai;
      8'h05:  key15 <= #delay des_datai;
      8'h06:  key16 <= #delay des_datai;
      8'h07:  key17 <= #delay des_datai;
      8'h08:  key20 <= #delay des_datai;
      8'h09:  key21 <= #delay des_datai;
      8'h0a:  key22 <= #delay des_datai;
      8'h0b:  key23 <= #delay des_datai;
      8'h0c:  key24 <= #delay des_datai;
      8'h0d:  key25 <= #delay des_datai;
      8'h0e:  key26 <= #delay des_datai;
      8'h0f:  key27 <= #delay des_datai;
      8'h10:  key30 <= #delay des_datai;
      8'h11:  key31 <= #delay des_datai;
      8'h12:  key32 <= #delay des_datai;
      8'h13:  key33 <= #delay des_datai;
      8'h14:  key34 <= #delay des_datai;
      8'h15:  key35 <= #delay des_datai;
      8'h16:  key36 <= #delay des_datai;
      8'h17:  key37 <= #delay des_datai;
      8'h18:  datain_00 <= #delay des_datai;
      8'h19:  datain_01 <= #delay des_datai;
      8'h1a:  datain_02 <= #delay des_datai;
      8'h1b:  datain_03 <= #delay des_datai;
      8'h1c:  datain_04 <= #delay des_datai;
      8'h1d:  datain_05 <= #delay des_datai;
      8'h1e:  datain_06 <= #delay des_datai;
      8'h1f:  datain_07 <= #delay des_datai;   
     endcase             

always @(posedge clk)
   if (rst)
     begin       
        des_datao <= #delay 8'h00;            
     end 
   else if(done_temp1)          
     case(out_cnt)
      8'h18:  des_datao <= #delay dataout_00;
      8'h19:  des_datao <= #delay dataout_01;
      8'h1a:  des_datao <= #delay dataout_02; 
      8'h1b:  des_datao <= #delay dataout_03;
      8'h1c:  des_datao <= #delay dataout_04;
      8'h1d:  des_datao <= #delay dataout_05; 
      8'h1e:  des_datao <= #delay dataout_06;
      8'h1f:  des_datao <= #delay dataout_07;
     endcase
     
//word address  of reading data 
always @(posedge clk)
    if (rst)        
        des_addr_r <= #delay 8'h00;                      
    else if (des_en_delay1)        
        des_addr_r <= #delay des_addr_r + 1;                       
    else if (done_temp1)   
        des_addr_r <= #delay 8'h00;

//word address  of writting data 
always @(posedge clk)
    if (rst)        
        des_addr_w <= #delay 8'h17;                  
    else if (done_temp1)        
        des_addr_w <= #delay des_addr_w + 1;
    
        
//mux des_addr_r or des_addr_w
assign des_addr  =  done_temp1? des_addr_w:des_addr_r;

//key  
assign	key1 = {key17[7:1],key16[7:1],key15[7:1],key14[7:1],key13[7:1],key12[7:1],key11[7:1],key10[7:1] };
assign	key2 = {key27[7:1],key26[7:1],key25[7:1],key24[7:1],key23[7:1],key22[7:1],key21[7:1],key20[7:1] };
assign	key3 = {key37[7:1],key36[7:1],key35[7:1],key34[7:1],key33[7:1],key32[7:1],key31[7:1],key30[7:1] };

//data
assign  datain = {datain_07,datain_06,datain_05,datain_04,datain_03,datain_02,datain_01,datain_00};
assign  dataout_07 = dataout[63:56];
assign  dataout_06 = dataout[55:48];
assign  dataout_05 = dataout[47:40];
assign  dataout_04 = dataout[39:32];
assign  dataout_03 = dataout[31:24];
assign  dataout_02 = dataout[23:16];
assign  dataout_01 = dataout[15:8];
assign  dataout_00 = dataout[7:0];

des3_cipher  des3__cipher_dut(.cipdataout(cipdataout),.cipdone(cipdone),.datain(datain),
               .key1(key1),.key2(key2),.key3(key3),
               .cipen(cipen),.des3(des3),.rst(rst),.clk(clk),
               .load_1(load_1),.load_2(load_2),.load_3(load_3),
               .done_1(done_1),.done_2(done_2),.done_3(done_3));
               
des3_inv_cipher  des3__inv_cipher_dut(.invdataout(invdataout),.invdone(invdone),.datain(datain),
               .key1(key1),.key2(key2),.key3(key3),
               .inven(inven),.des3(des3),.rst(rst),.clk(clk));               

//MUX des3_decode
assign dataout = des_decode ? invdataout:cipdataout;
assign done = des_decode ? invdone:cipdone;
assign cipen = des_decode ? Low:en;
assign inven = des_decode ? en:Low;      

 
 
 
endmodule