aes.v

aes加密算法实现

`timescale 1ns / 10ps

module  aes       (clk, 
                   rst, 
                   kld0, 
                   ld, 
                   done,
                   key, 
                   text_in, 
                   text_out
                   );
                   
input	clk;
input   	rst;
input   	ld;    //load plain text[ 127: 0]
input   	kld0;   //load key[ 31: 0]
input	  [31:0]	key;
input	  [31:0]	text_in;

output  done;
output	[127:0]	text_out;

reg  ld3_r;        
reg  done;
reg done1;
reg  [2:0] cnt;    //count 5 cycles per round
reg  [7:0] dcnt;   //count 54 cycles all 11 rounds
reg [31:0] sa0,sa1,sa2,sa3;
reg  [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
reg  [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
reg  [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
reg  [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
reg  [7:0] sa0_sr, sa1_sr, sa2_sr, sa3_sr;  //input data of sbox
reg  kld1,kld2,kld3;
reg [127:0]text_out;



wire [31:0] key_out;
wire [31:0] text;
wire  [7:0] w0, w1, w2, w3;
wire  [7:0] sa0_sub, sa1_sub, sa2_sub, sa3_sub;
wire [31:0] sa_mc;
wire [31:0] sa_next;
wire  kld0,ld;

////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @( posedge clk)
	if( rst )	
		ld3_r <= #1 1'b0;
	else 	
	                 ld3_r <= #1 kld3;
	
always @( posedge clk)
	if( rst )	
			dcnt <= #1 8'd0;
	else if(ld)		
			dcnt <= #1 8'd53;
	else if(|dcnt)  
			dcnt <= #1 dcnt - 8'd1;
	
always @( posedge clk)
	if( rst )	
		cnt <= #1 3'd0;
	else 
		if( ld )
			cnt <= #1 3'd2;
		else if( cnt==3'd5 )
			cnt <= #1 3'd1;
		else if( |cnt )
			cnt <= #1 cnt+1;	
	
	
always @( posedge clk) 
	begin
		if( rst )
			done1 <= #1 1'b0;
		else if( dcnt==8'd4 | dcnt==8'd3 | dcnt==8'd2 | dcnt==8'd1 )
			done1 <= #1 1'b1;
		else
			done1 <= #1 1'b0;			
	end
	
	
always @( posedge clk) 
	begin
		if( rst )
			done <= #1 1'b0;
		else if( dcnt==8'd0 )
			done <= #1 1'b1;
		else
			done <= #1 1'b0;			
	end
		
always @( posedge clk) 
	begin
		if( rst )
		      begin
			
			kld1 <= #1 1'b0;
			kld2 <= #1 1'b0;
			kld3 <= #1 1'b0;
			end
		else 
		begin
		 kld1<= #1kld0;	
		  kld2<= #1kld1;
		   kld3<= #1kld2;
		end   	
	end
////////////////////////////////////////////////////////////////////
//
// Initial Permutation (AddRoundKey)
//

always @( posedge clk)	
	begin
		if( rst )
			sa0 <= #1 32'b0;
		else 
		  if( kld0 )
				sa0 <= #1 text_in ^ key;
		  else if( cnt==3'd2 & !kld1 )
				sa0 <= #1 sa_next;
			else
		  	sa0 <= #1 sa0;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa1 <= #1 32'b0;
		else
			if( kld1 )
				sa1 <= #1 text_in ^ key;
			else if( cnt==3'd3 & !kld2  )
				sa1 <= #1 sa_next;
			else
		  	sa1 <= #1 sa1;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa2 <= #1 32'b0;
		else
			if( kld2 )
				sa2 <= #1 text_in ^ key;
			else if( cnt==3'd4 & !kld3  )
				sa2 <= #1 sa_next;
			else
		  	sa2 <= #1 sa2;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa3 <= #1 32'b0;
		else
			if( kld3 )
				sa3 <= #1 text_in ^ key;
			else
		  	sa3 <= #1 sa3;
	end
	
//ShiftRows
always @( posedge clk)	
	begin
		if( rst )
			sa00_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )
				sa00_sr <= #1 sa0[31:24];	
			else
		  	sa00_sr <= #1 sa00_sr;
	end
	
always @( posedge clk)	
	begin
		if( rst )
			sa01_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )
				sa01_sr <= #1 sa1[31:24];	
			else
		  	sa01_sr <= #1 sa01_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa02_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )
				sa02_sr <= #1 sa2[31:24];	
			else
		  	sa02_sr <= #1 sa02_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa03_sr <= #1 8'b0;
		else 
			if( ld3_r )
				sa03_sr <= #1 sa3[31:24];	
			else if( cnt==3'd5 )
				sa03_sr <= #1 sa_next[31:24];	
			else
		  	sa03_sr <= #1 sa03_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa20_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )
				sa20_sr <= #1 sa2[15:08];
			else
		  	sa20_sr <= #1 sa20_sr;
	end
	
always @( posedge clk)	
	begin
		if( rst )
			sa21_sr <= #1 8'b0;
		else 
			if( ld3_r )
				sa21_sr <= #1 sa3[15:08];	
			else if( cnt==3'd5 )
				sa21_sr <= #1 sa_next[15:08];
			else
		  	sa21_sr <= #1 sa21_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa22_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )
				sa22_sr <= #1 sa0[15:08];
			else
		  	sa22_sr <= #1 sa22_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa23_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )
				sa23_sr <= #1 sa1[15:08];
			else
		  	sa23_sr <= #1 sa23_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa10_sr <= #1 8'b0;
		else if(  cnt==3'd5 )
				sa10_sr <= #1 sa1[23:16];
			
			   //deleted by gw 2007.8.1 
			
			
			else
		  	sa10_sr <= #1 sa10_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa11_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )begin
					sa11_sr <= #1 sa2[23:16];
			end
			else
		  	sa11_sr <= #1 sa11_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa12_sr <= #1 8'b0;
		else 
			if( ld3_r )
				sa12_sr <= #1 sa3[23:16];	
			else if( cnt==3'd5 )
					sa12_sr <= #1 sa_next[23:16];  //deleted by gw 2007.8.1 
				
			else
		  	sa12_sr <= #1 sa12_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa13_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )
					sa13_sr <= #1 sa0[23:16];
				
			else
		  	sa13_sr <= #1 sa13_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa30_sr <= #1 8'b0;
		else 
			if( ld3_r )
				sa30_sr <= #1 sa3[07:00];	
			else if( cnt==3'd5 )
					sa30_sr <= #1 sa_next[07:00];  //deleted by gw 2007.8.1 
				
			else
		  	sa30_sr <= #1 sa30_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa31_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )
					sa31_sr <= #1 sa0[07:00]; //deleted by gw 2007.8.1 
				
			else
		  	sa31_sr <= #1 sa31_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa32_sr <= #1 8'b0;
		else 
			if( ld3_r )
				sa32_sr <= #1 sa1[07:00];	
			else if(  cnt==3'd5 )
					sa32_sr <= #1 sa1[07:00]; //deleted by gw 2007.8.1 
				
			else
		  	sa32_sr <= #1 sa32_sr;
	end

always @( posedge clk)	
	begin
		if( rst )
			sa33_sr <= #1 8'b0;
		else 
			if( cnt==3'd5 )
					sa33_sr <= #1 sa2[07:00]; //deleted by gw 2007.8.1 
				
			else
		  	sa33_sr <= #1 sa33_sr;
	end


/*****************select input data of sbox********************/
always @( posedge clk)
	begin
		if( rst )
			sa0_sr <= #1 8'b0;
		else 
			case( cnt )
				3'd5: sa0_sr <= #1 w0;
				3'd1: sa0_sr <= #1 sa00_sr;  
				3'd2: sa0_sr <= #1 sa01_sr;  
				3'd3: sa0_sr <= #1 sa02_sr;  
				3'd4: sa0_sr <= #1 sa03_sr;  
				default:sa0_sr <= #1 8'b0;
			endcase
	end

always @( posedge clk)
	begin
		if( rst )
			sa1_sr <= #1 8'b0;
		else
			case( cnt )
				3'd5: sa1_sr <= #1 w1;
				3'd1: sa1_sr <= #1 sa10_sr;  
				3'd2: sa1_sr <= #1 sa11_sr;  
				3'd3: sa1_sr <= #1 sa12_sr;  
				3'd4: sa1_sr <= #1 sa13_sr;  
				default:sa1_sr <= #1 8'b0;
			endcase
	end

always @( posedge clk)
	begin
		if( rst )
			sa2_sr <= #1 8'b0;
		else
			case( cnt )
				3'd5: sa2_sr <= #1 w2;
				3'd1: sa2_sr <= #1 sa20_sr;  
				3'd2: sa2_sr <= #1 sa21_sr;  
				3'd3: sa2_sr <= #1 sa22_sr;  
				3'd4: sa2_sr <= #1 sa23_sr;  
				default:sa2_sr <= #1 8'b0;
			endcase
	end

always @( posedge clk)
	begin
		if( rst )
			sa3_sr <= #1 8'b0;
		else
			case( cnt )
				3'd5: sa3_sr <= #1 w3;
				3'd1: sa3_sr <= #1 sa30_sr;  
				3'd2: sa3_sr <= #1 sa31_sr;  
				3'd3: sa3_sr <= #1 sa32_sr;  
				3'd4: sa3_sr <= #1 sa33_sr;  
				default:sa3_sr <= #1 8'b0;
			endcase
	end

always @( posedge clk)
                 begin
                            if (rst)
                                      text_out<=  128'hx;
                           else if(done1)
                                 case (dcnt)           
                                            8'd3:text_out[127:96]<=text;   
                                            8'd2:text_out[95:64]<=text;   
                                            8'd1:text_out[63:32]<=text;   
                                            8'd0:text_out[31:0]<=text;
		default:text_out<=  128'hx;
	endcase	
                 end

//Mixcolumns
assign sa_mc =  mix_col( sa0_sub, sa1_sub, sa2_sub, sa3_sub ) ;

//AddRoundKey
assign sa_next = sa_mc ^ key_out;

////////////////////////////////////////////////////////////////////
//
// Final text output
//

assign text[031:024] = sa0_sub ^ key_out[31:24];
assign text[023:016] = sa1_sub ^ key_out[23:16];
assign text[015:008] = sa2_sub ^ key_out[15:08];
assign text[007:000] = sa3_sub ^ key_out[07:00];

////////////////////////////////////////////////////////////////////
//
// Generic Functions
//

function [31:0] mix_col;
input	[7:0]	a3,a2,a1,a0;
begin
mix_col[31:24]=xtime(a3)^xtime(a2)^a2^a1^a0;
mix_col[23:16]=a3^xtime(a2)^xtime(a1)^a1^a0;
mix_col[15:08]=a3^a2^xtime(a1)^xtime(a0)^a0;
mix_col[07:00]=xtime(a3)^a3^a2^a1^xtime(a0);
end
endfunction

function [31:0] inv_mc;
input	[7:0]	b3,b2,b1,b0;
reg  [31:0] mc;
begin
mc=mix_col(b3,b2,b1,b0);
inv_mc[31:24]=five(mc[31:24])^four(mc[15:08]);
inv_mc[23:16]=five(mc[23:16])^four(mc[07:00]);
inv_mc[15:08]=five(mc[15:08])^four(mc[31:24]);
inv_mc[07:00]=five(mc[07:00])^four(mc[23:16]);
end
endfunction

function [7:0] xtime;
input [7:0] b; 
	xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
endfunction

function [7:0] four;
input [7:0] a;
reg [7:0] two;
begin
two=xtime(a);four=xtime(two);
end
endfunction

function [7:0] five;
input [7:0] a;
begin
five=a^four(a);
end
endfunction

////////////////////////////////////////////////////////////////////
//
// Modules
//

aes_key_expand_128 u0(
	.clk(		clk	),
	.rst(   rst ),
	.key(		key	),
	.cnt(   cnt ),
	.kld0(		kld0	),
	.wi_0(	sa0_sub	),
	.wi_1(	sa1_sub	),
	.wi_2(	sa2_sub	),
	.wi_3(	sa3_sub	),
	.wo_0(	w0	),
	.wo_1(	w1	),
	.wo_2(	w2	),
	.wo_3(	w3	),
	.key_out(	key_out	));

aes_sbox us0(	.a(	sa0_sr	), .d(	sa0_sub	));
aes_sbox us1(	.a(	sa1_sr	), .d(	sa1_sub	));
aes_sbox us2(	.a(	sa2_sr	), .d(	sa2_sub	));
aes_sbox us3(	.a(	sa3_sr	), .d(	sa3_sub	));

endmodule