aes_key_expand_128.v

aes加密算法实现

`timescale 1ns / 10ps

module aes_key_expand_128(	clk,
                          		rst, 
			kld0,  
			key, 
			cnt, 
			wo_0, wo_1, wo_2, wo_3,
			wi_0, wi_1, wi_2, wi_3,
			key_out);
input		clk;
input   		rst;
input		kld0;
input	 [31:0]	key;
input   	[2:0]	 cnt;
input   	[7:0]	 wi_0, wi_1, wi_2, wi_3; 
output	[7:0]	wo_0, wo_1, wo_2, wo_3;
output 	[31:0] 	key_out;

reg	[31:0]	key0, key1, key2, key3;
reg	[31:0]	rcon;
reg	[31:0]  key_out;
reg kld1,kld2,kld3;

wire  	 [2:0]  	cnt;
wire  	[31:0]  	subword;
wire	 [7:0]	wo_0, wo_1, wo_2, wo_3;

assign wo_0 = key3[23:16];
assign wo_1 = key3[15:08];
assign wo_2 = key3[07:00];
assign wo_3 = key3[31:24];

assign subword = { wi_0, wi_1, wi_2, wi_3 };

always @( cnt or key0 or key1 or key2 or key3 )
	begin
		case( cnt )
			3'd2: key_out <= #1 key0;
			3'd3: key_out <= #1 key1;
			3'd4: key_out <= #1 key2;
			3'd5: key_out <= #1 key3;
			default:key_out <= #1 32'bz;
		endcase
	end
always @( posedge clk) 
	begin
		if( rst )
		      begin
         kld1 <= #1 1'b0;
			kld2 <= #1 1'b0;
			kld3 <= #1 1'b0;
			end
		else 
		begin
		 kld1<= #1kld0;	
		  kld2<= #1kld1;
		   kld3<= #1kld2;
		end   	
	end
always @( posedge clk)	
	begin
		if( rst )
			key0 <= #1 32'b0;
		else
			if( kld0 )
				key0 <= #1 key;
			else if( cnt==3'd1 )
				key0 <= #1 key0^subword^rcon;
	end

always @( posedge clk)	
	begin
		if( rst )
			key1 <= #1 32'b0;
		else
			if( kld1 )
				key1 <= #1 key;
			else if( cnt==3'd2 )
				key1 <= #1 key1^key0;
	end

always @( posedge clk)	
	begin
		if( rst )
			key2 <= #1 32'b0;
		else
			if( kld2 )
				key2 <= #1 key;
			else if( cnt==3'd3  )
				key2 <= #1 key2^key1;
	end
	
always @( posedge clk)	
	begin
		if( rst )
			key3 <= #1 32'b0;
		else
			if( kld3 )
				key3 <= #1 key;
			else if( cnt==3'd4  )
				key3 <= #1 key3^key2;
	end
	
//Generate Rcon 

reg	[3:0]	rcnt;

always @( posedge clk)
	begin
		if(rst)		
			rcon <= #1 32'b0;
		else		    
			rcon <= #1 frcon(rcnt);
	end
	
always @( posedge clk)
	begin
		if( rst )		
			rcnt <= #1 4'd0;
		else if(kld0)                      //added by hy
		        rcnt <= #1 4'd0;
		else if( cnt==3'd4 )		
			rcnt <= #1 rcnt+1;
		else
			rcnt <= #1 rcnt;
	end

function [31:0]	frcon;
input	[3:0]	i;
case(i)	// synopsys parallel_case
   4'h1: frcon=32'h01_00_00_00;
   4'h2: frcon=32'h02_00_00_00;
   4'h3: frcon=32'h04_00_00_00;
   4'h4: frcon=32'h08_00_00_00;
   4'h5: frcon=32'h10_00_00_00;
   4'h6: frcon=32'h20_00_00_00;
   4'h7: frcon=32'h40_00_00_00;
   4'h8: frcon=32'h80_00_00_00;
   4'h9: frcon=32'h1b_00_00_00;
   4'ha: frcon=32'h36_00_00_00;
   default: frcon=32'h00_00_00_00;
endcase
endfunction

endmodule