em78x468xx.h

中央空调控制器全套资料

/********************************************************
 *	Header file for the Elan			     			*
 *	EM78P468N chip					     				*	
 *	Tilte:       EM78x468x include file                 * 
 * 	Description: The Definition of EM78x468x Registers  *
 * 	Company:     ELAN MICROELECTRONICS (SZ) LTD.        * 
 * 	Author:      HongXi.Tang			     			*
 * 	Date:        10/05/2005                             *
 *	Version:     v1.0                                   *
 ********************************************************/
 
static unsigned int TCC		@0x01:rpage 0;
static unsigned int PC      @0x02:rpage 0;
static unsigned int STATUS  @0x03:rpage 0;
static unsigned int RSR		@0x04:rpage 0;
static unsigned int PORT5   @0x05:rpage 0;
static unsigned int PORT6   @0x06:rpage 0;
static unsigned int PORT7   @0x07:rpage 0;
static unsigned int PORT8	@0x08:rpage 0;
static unsigned int LCDCR	@0x09:rpage 0;//LCD control register
static unsigned int LCD_ADDR	@0x0A:rpage 0;//LCD address
static unsigned int LCD_DB		@0x0B:rpage 0;//LCD data buffer
static unsigned int CNTER		@0x0C:rpage 0;//LVD control & counter enable
static unsigned int SBPCR		@0x0D:rpage 0;//system&PLL/Booster frequency
static unsigned int IRCR		@0x0E:rpage 0;//IR and PORT5 Setting Control Register
static unsigned int ISR			@0x0F:rpage 0;//interrupt status register

static io unsigned int P5CR @0x05:iopage 0;
static io unsigned int P6CR @0x06:iopage 0;
static io unsigned int P7CR @0x07:iopage 0;
static io unsigned int P8CR @0x08:iopage 0;
static io unsigned int RAM_ADDR	@0x09:iopage 0;//128 byte RAM address
static io unsigned int RAM_DB 	@0x0A:iopage 0;//128 byte RAM buffer
static io unsigned int CNT1PR 	@0x0B:iopage 0;//Counter1 preset
static io unsigned int CNT2PR 	@0x0C:iopage 0;//Counter2 preset
static io unsigned int HPWTPR 	@0x0D:iopage 0;//high-pulse width timer preset
static io unsigned int LPWTPR 	@0x0E:iopage 0;//low-pulse width timer preset
static io unsigned int IMR 		@0x0F:iopage 0;//interrupt mask register

static io unsigned int WUCR		@0x06:iopage 1;//Wake up & P5.7 sink current
static io unsigned int TCCCR 	@0x07:iopage 1;//TCC & INT0 control register
static io unsigned int WDTCR 	@0x08:iopage 1;//WDT control register
static io unsigned int CNT12CR 	@0x09:iopage 1;//counter1,2 control
static io unsigned int HLPWTCR 	@0x0A:iopage 1;//high/low pulse width timer control
static io unsigned int P6PH 	@0x0B:iopage 1;//port6 pull-high control
static io unsigned int P6OD 	@0x0C:iopage 1;//port6 open-drain control
static io unsigned int P8PH 	@0x0D:iopage 1;//port8 pull-high control
static io unsigned int P6PL 	@0x0E:iopage 1;//port8 pull-down control

/*	STATUS bits	*/
static bit PS1 @0x03@6:rpage 0;
static bit PS0 @0x03@5:rpage 0;	//page select bits
static bit T   @0x03@4:rpage 0;
static bit P   @0x03@3:rpage 0;
static bit Z   @0x03@2:rpage 0;
static bit DC  @0x03@1:rpage 0;
static bit C   @0x03@0:rpage 0;

/*	R5 bits	*/
static bit R57 @0x05@7:rpage 0;
static bit R56 @0x05@6:rpage 0;
static bit R55 @0x05@5:rpage 0;
static bit R54 @0x05@4:rpage 0;
static bit IOCPAGE @0x05@0:rpage 0;//change IOC8 ~ IOCF to another page, 0/1 => page0 / page1

static bit R67	@0x06@7:rpage 0;
static bit R66	@0x06@6:rpage 0;
static bit R65  @0x06@5:rpage 0;
static bit R64	@0x06@4:rpage 0;
static bit R63  @0x06@3:rpage 0;
static bit R62	@0x06@2:rpage 0;
static bit R61	@0x06@1:rpage 0;
static bit R60	@0x06@0:rpage 0;

static bit R77	@0x07@7:rpage 0;
static bit R76	@0x07@6:rpage 0;
static bit R75	@0x07@5:rpage 0;
static bit R74	@0x07@4:rpage 0;
static bit R73	@0x07@3:rpage 0;
static bit R72	@0x07@2:rpage 0;
static bit R71	@0x07@1:rpage 0;
static bit R70	@0x07@0:rpage 0;

static bit R87	@0x08@7:rpage 0;
static bit R86	@0x08@6:rpage 0;
static bit R85	@0x08@5:rpage 0;
static bit R84	@0x08@4:rpage 0;
static bit R83	@0x08@3:rpage 0;
static bit R82	@0x08@2:rpage 0;
static bit R81	@0x08@1:rpage 0;
static bit R80	@0x08@0:rpage 0;

/* lcd control register	*/
static bit LCDBS 	@0x09@7:rpage 0;
//LCD bias select bit, 0/1=>(1/2 bias) / (1/3 bias)
static bit DS1 		@0x09@6:rpage 0;
static bit DS0 		@0x09@5:rpage 0;
//LCD duty select
//DS1 DS0 LCD duty
// 0   0  1/2 duty
// 0   1  1/3 duty
// 1   X  1/4 duty
static bit LCDEN 	@0x09@4:rpage 0;
//LCD enable bit: 0/1 -> LCD circuit disable/enable. When LCD function is disabled,
//all common/segment outputs are set to ground (GND) level.
//not used--
static bit LCDTYPE 	@0x09@2:rpage 0;
//LCD drive waveform type select bit
//0: A type waveform
//1: B type waveform
static bit LCDF1 	@0x09@1:rpage 0;
static bit LCDF0	@0x09@0:rpage 0;
//LCD clock pre-scaler ratio control bit
//LCD frame frequency (Fs=32.768KHz) LCDF1 LCDF0 1/2 duty 1/3 duty 1/4 duty
// 0   0     Fs/(256*2)=64.0 Fs/(172*3)=63.5 Fs/(128*4) =64.0
// 0   1     Fs/(280*2)=58.5 Fs/(188*3)=58.0 Fs/(140*4) =58.5
// 1   0     Fs/(304*2)=53.9 Fs/(204*3)=53.5 Fs/(152*4) =53.9
// 1   1     Fs/(232*2)=70.6 Fs/(156*3)=70.0 Fs/(116*4) =70.6

/*	LVD Control and Counter Enable Register	*/
static bit LVDEN	@0x0c@7:rpage 0;
//Enable low voltage detector.
//1: enable LVD function.
//0: disable LVD function.
static bit LV 		@0x0c@6:rpage 0;
//Low voltage detector. This is a read only bit. When the VDD pin voltage is lower than
//Vdet (selected by LVD0), this bit will be cleared.
//0: the low voltage is detected.
//1: the low voltage is not detected or LVD function is disabled.
static bit LVDF		@0x0c@5:rpage 0;
//interrupt flag of Low voltage detector.
static bit LVD0 	@0x0c@4:rpage 0;
//the low voltage detector select bits
//LVD0 Vdet
// 0    2.1 V
// 1    2.3 V
//LVD0=0: if Vdet voltage drops lower than 2.1V or rises higher than 2.3V, then interrupt occurs.
//LVD0=1: if Vdet voltage drops lower than 2.3V or rises higher than 2.5V, then interrupt occur.
static bit LPWTEN 	@0x0c@3:rpage 0;
//low pulse width time enable bit, 0/1 => disable/enable
static bit HPWTEN 	@0x0c@2:rpage 0;
//high pulse width timer enable bit, 0/1 => disable/enable
static bit CNT2EN 	@0x0c@1:rpage 0;
//counter 2 enable bit, 0/1 => disable/enable
static bit CNT1EN	@0x0c@0:rpage 0;
//counter 1 enable bit, 0/1 => disable/enable

/*	System Clock, Booster Frequency, and PLL Frequency 
Control	Registers	*/
static bit CLK2 	@0x0d@6:rpage 0;
static bit CLK1 	@0x0d@5:rpage 0;
static bit CLK0 	@0x0d@4:rpage 0;
static bit IDLE 	@0x0d@3:rpage 0;
static bit BF1 		@0x0d@2:rpage 0;
static bit BF0 		@0x0d@1:rpage 0;
static bit CPUS		@0x0d@0:rpage 0;
/*
Bit 6~4 (CLK2~0): 
main clock select bit for PLL mode (code option select)
CLK2 CLK1 CLK0 Main clock
  0   0    0    32.768K*130=4.26 MHz
  0   0    1    32.768K*65=2.13 MHz
  0   1    0    2.13MHz/2
  0   1    1    2.13MHz/4
  1   --   --   32.768K*244=8 MHz
Bit 3 (IDLE): 
idle mode enable bit. This bit will decide the intended mode of the SLEP instruction.
IDLE=”0”+SLEP instruction => sleep mode
IDLE=”1”+SLEP instruction => idle mode
Bit 2,1 (BF1, 0): 
LCD booster frequency select bit
BF1 BF0 Booster frequency
 0   0     Fs
 0   1     Fs/4
 1   0     Fs/8
 1   1     Fs/16
Bit 0 (CPUS): 
CPU oscillator source select, 0/1=> sub-oscillator (Fs)/ main oscillator (Fm)
When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator is stopped.
*/

/*	IR Control and PORT5 Function Pins Set Register	*/
static bit IRE	@0x0e@7:rpage 0;
static bit HF	@0x0e@6:rpage 0;
static bit LGP	@0x0e@5:rpage 0;
//not used
static bit IROUTE	@0x0e@3:rpage 0;
static bit TCCE		@0x0e@2:rpage 0;
static bit EINT1	@0x0e@1:rpage 0;
static bit EINT0	@0x0e@0:rpage 0;
/*
Bit 7 	Bit 6 	Bit 5 	Bit 4 	Bit 3 	Bit 2 	Bit 1 	Bit 0
 IRE 	  HF     LGP      --    IROUTE   TCCE   EINT1   EINT0
 
Bit 7 (IRE): Infrared Remote Enable bit
0: Disable IRE. Disable H/W Modulator Function. IROUT pin fixed to high level
1: Enable IRE. Enable H/W Modulator Function. Pin 6.7 defined as IROUT.
Bit 6 (HF): High frequency.
0: For PWM application, IROUT waveform is created according to high-pulse and low-pulse
width time as determined by the high pulse and low pulse width timers respectively.
1: For IR application mode, the low time sections of the generated pulse is modulated with
the frequency Fcarrier,
Bit 5 (LGP): long pulse.
0: the high-pulse timer register and low-pulse width timer is valid.
1: The high-pulse width timer register is ignored. So the IROUT waveform is dependent on
low-pulse width timer register only
Bit 4: Not used
Bit 3 (IROUTE): control bit is used to define the function of P5.7 (IROUT) pin.
0: P5.7, bi-directional I/O pin.
1: IROUT, in this case, the I/O control bit of P5.7 (bit 7 of IOC5) must be set to “0”
Bit 2 (TCCE): control bit is used to define the function of P5.6 (TCC) pin.
0: P5.6, bi-directional I/O pin.
1: TCC, external input pin of TCC. In this case, the I/O control bit of P5.6 (bit 6 of IOC5)
must be set to “1”
Bit 1 (EINT1): control bit is used to define the function of P5.5 (INT1) pin.
0: P5.5, bi-directional I/O pin.
1: INT1, external interrupt pin. In this case, the I/O control bit of P5.5 (bit 5 of IOC5) must be
set to “1”
Bit 0 (EINT0): control bit is used to define the function of P5.4 (INT0) pin.
0: P5.4, bi-directional I/O pin.
1: INT0, external interrupt pin. In this case, the I/O control bit of P5.4 (bit 4 of IOC5) must be
set to “1”
*/

/*	Interrupt Status Register	*/
static bit ICIF		@0x0f@7:rpage 0;
static bit LPWTF 	@0x0f@6:rpage 0;
static bit HPWTF 	@0x0f@5:rpage 0;
static bit CNT2F	@0x0f@4:rpage 0;
static bit CNT1F 	@0x0f@3:rpage 0;
static bit INT1F 	@0x0f@2:rpage 0;
static bit INT0F 	@0x0f@1:rpage 0;
static bit TCIF		@0x0f@0:rpage 0;
/*
Bit 7 (ICIF): Port 6, Port 8, input status changed interrupt flag. Set when PORT6, PORT8 input
changes.
Bit 6 (LPWTF): interrupt flag of internal low-pulse width timer underflow.
Bit 5 (HPWTF): interrupt flag of internal high-pulse width timer underflow.
Bit 4 (CNT2): interrupt flag of internal counter 2 under-flow.
Bit 3 (CNT1): interrupt flag of internal counter 1 underflow.
Bit 2 (INT1F): external INT1 pin interrupt flag.
Bit 1 (INT0F): external INT0 pin interrupt flag.
Bit 0 (TCIF): TCC timer overflow interrupt flag. Set when TCC timer overflows.
*/