📄 system.log
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-xl-mode-executable \ mb-size TestApp_Memory/executable.elf text data bss dec hex filename 3768 324 8 4100 1004 TestApp_Memory/executable.elfDone.At Local date and time: Wed Nov 01 18:28:27 2006Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make program; exit;" Started...make: Nothing to be done for `program'.Done.At Local date and time: Wed Nov 01 18:28:36 2006Command xbash -q -c "cd /cygdrive/d/mb-jpeg/; /usr/bin/make -f system.make bits; exit;" Started...****************************************************Creating system netlist for hardware specification..****************************************************platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xst system.mhsRelease Xilinx EDK 7.1.2 - platgen EDK_H.12.5.1Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: platgen -p xc2vp30ff896-7 -lang vhdl -lp D:/XilinxXUP/lib/ -st xstsystem.mhs Parse system.mhs ...Read MPD definitions ...Sourcing tcl fileC:/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v4_00_a/data/microblaze_v2_1_0.tcl ...Sourcing tcl fileC:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_v10_v2_1_0.tcl...Sourcing tcl fileC:/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v1_00_b/data/lmb_bram_if_cntlr_v2_1_0.tcl ...Sourcing tcl fileC:/EDK/hw/XilinxProcessorIPLib/pcores/opb_sysace_v1_00_c/data/opb_sysace_v2_1_0.tcl ...Sourcing tcl fileC:/EDK/hw/XilinxProcessorIPLib/pcores/opb_ddr_v2_00_b/data/opb_ddr_v2_1_0.tcl...Overriding IP level properties ...microblaze (microblaze_0) -C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.mpd:60 - tool overriding c_family value virtex2 to virtex2pmicroblaze (microblaze_0) -C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.mpd:61 - tool overriding c_instance value microblaze to microblaze_0microblaze (microblaze_0) -C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.mpd:90 - tcl overriding C_ADDR_TAG_BITS value 17 to 0microblaze (microblaze_0) -C:\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v4_00_a\data\microblaze_v2_1_0.mpd:97 - tcl overriding C_DCACHE_ADDR_TAG value 17 to 0opb_mdm (debug_module) -C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_mdm_v2_00_a\data\opb_mdm_v2_1_0.mpd:38- tool overriding c_family value virtex2 to virtex2pbram_block (lmb_bram) -C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd:39 - tool overriding c_family value virtex2 to virtex2popb_ddr (ddr_256mb_32mx64_rank1_row13_col10_cl2_5) -C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ddr_v2_00_b\data\opb_ddr_v2_1_0.mpd:42- tool overriding c_family value virtex2 to virtex2pdcm_module (dcm_0) -C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.mpd:56 - tool overriding c_family value virtex2 to virtex2pdcm_module (dcm_1) -C:\EDK\hw\XilinxProcessorIPLib\pcores\dcm_module_v1_00_a\data\dcm_module_v2_1_0.mpd:56 - tool overriding c_family value virtex2 to virtex2pPerforming IP level DRCs on properties...Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...Address Map for Processor microblaze_0 (0x00000000-0x00001fff) dlmb_cntlr dlmb (0x00000000-0x00001fff) ilmb_cntlr ilmb (0x30000000-0x3fffffff) DDR_256MB_32MX64_rank1_row13_col10_cl2_5 mb_opb (0x40600000-0x4060ffff) RS232_Uart_1 mb_opb (0x41400000-0x4140ffff) debug_module mb_opb (0x41800000-0x4180ffff) SysACE_CompactFlash mb_opbCheck platform configuration ...opb_v20 (mb_opb) - D:\mb-jpeg\system.mhs:74 - 2 master(s) : 4 slave(s)lmb_v10 (ilmb) - D:\mb-jpeg\system.mhs:100 - 1 master(s) : 1 slave(s)lmb_v10 (dlmb) - D:\mb-jpeg\system.mhs:108 - 1 master(s) : 1 slave(s)Check port drivers...Check platform address map ...Overriding system level properties ...opb_v20 (mb_opb) -C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_v20_v1_10_c\data\opb_v20_v2_1_0.mpd:36- tool overriding c_num_masters value 4 to 2lmb_v10 (ilmb) -C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36- tool overriding c_lmb_num_slaves value 4 to 1lmb_v10 (dlmb) -C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_1_0.mpd:36- tool overriding c_lmb_num_slaves value 4 to 1lmb_bram_if_cntlr (dlmb_cntlr) -C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000lmb_bram_if_cntlr (ilmb_cntlr) -C:\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v1_00_b\data\lmb_bram_if_cntlr_v2_1_0.mpd:42 - tool overriding c_mask value 0x00800000 to 0x10c00000bram_block (lmb_bram) -C:\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd:35 - tool overriding c_memsize value 2048 to 8192Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...Sourcing tcl fileC:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...Performing System level DRCs on properties...Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...Sourcing tcl fileC:/EDK/hw/XilinxProcessorIPLib/pcores/ddr_v2_00_b/data/ddr_v2_1_0.tcl ...INFO: The DDR_256MB_32MX64_rank1_row13_col10_cl2_5 core has constraints automatically generated by XPS in implementation/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper/ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper.ucf.It can be overridden by constraints placed in the system.ucf file.Modify defaults ...Processing licensed instances ...Completion time: 0.00 secondsCreating hardware output directories ...Managing hardware (BBD-specified) netlist files ...Managing cache ...Elaborating instances ...bram_block (lmb_bram) - D:\mb-jpeg\system.mhs:134 - elaborating IPWriting HDL for elaborated instances ...Inserting wrapper level ...Completion time: 4.00 secondsConstructing platform-level signal connectivity ...Completion time: 3.00 secondsWriting (top-level) BMM ...Writing BMM - D:\mb-jpeg\implementation\system.bmmWriting (top-level and wrappers) HDL ...Generating synthesis project file ...Running XST synthesis ...INFO:MDT - The following instances are synthesized with XST. The MPD option IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.microblaze_0_wrapper (microblaze_0) - D:\mb-jpeg\system.mhs:54 - Running XSTsynthesismb_opb_wrapper (mb_opb) - D:\mb-jpeg\system.mhs:74 - Running XST synthesisdebug_module_wrapper (debug_module) - D:\mb-jpeg\system.mhs:82 - Running XSTsynthesisilmb_wrapper (ilmb) - D:\mb-jpeg\system.mhs:100 - Running XST synthesisdlmb_wrapper (dlmb) - D:\mb-jpeg\system.mhs:108 - Running XST synthesisdlmb_cntlr_wrapper (dlmb_cntlr) - D:\mb-jpeg\system.mhs:116 - Running XSTsynthesisilmb_cntlr_wrapper (ilmb_cntlr) - D:\mb-jpeg\system.mhs:125 - Running XSTsynthesislmb_bram_wrapper (lmb_bram) - D:\mb-jpeg\system.mhs:134 - Running XST synthesisrs232_uart_1_wrapper (rs232_uart_1) - D:\mb-jpeg\system.mhs:141 - Running XSTsynthesissysace_compactflash_wrapper (sysace_compactflash) - D:\mb-jpeg\system.mhs:157 -Running XST synthesisddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:174 - RunningXST synthesissysclk_inv_wrapper (sysclk_inv) - D:\mb-jpeg\system.mhs:218 - Running XSTsynthesisclk90_inv_wrapper (clk90_inv) - D:\mb-jpeg\system.mhs:227 - Running XSTsynthesisddr_clk90_inv_wrapper (ddr_clk90_inv) - D:\mb-jpeg\system.mhs:236 - Running XSTsynthesisdcm_0_wrapper (dcm_0) - D:\mb-jpeg\system.mhs:245 - Running XST synthesisdcm_1_wrapper (dcm_1) - D:\mb-jpeg\system.mhs:261 - Running XST synthesisRunning NGCBUILD ...ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper(ddr_256mb_32mx64_rank1_row13_col10_cl2_5) - D:\mb-jpeg\system.mhs:174 - RunningNGCBUILDRebuilding cache ...Total run time: 282.00 secondsRunning synthesis...bash -c "cd synthesis; ./synthesis.sh; cd .."WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 17 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!Release 7.1.02i - xst H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.--> TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput Format : MIXEDInput File Name : "system_xst.prj"---- Target ParametersTarget Device : xc2vp30ff896-7Output File Name : "../implementation/system.ngc"---- Source OptionsTop Module Name : system---- Target OptionsAdd IO Buffers : NO⌨️ 快捷键说明
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