system.ucf

source codes jpeg_vhdl

Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> LOC=W29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> LOC=T22;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> LOC=W28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> LOC=W27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> LOC=W26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> LOC=W25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> LOC=E30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> LOC=J29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> LOC=M30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> LOC=P29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> LOC=V23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> LOC=AA25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> LOC=AC25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> LOC=AH26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> LOC=C27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> LOC=D28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> LOC=D29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> LOC=D30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> LOC=H25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> LOC=H26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> LOC=E27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> LOC=E28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> LOC=J26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> LOC=G27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> LOC=G28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> LOC=G30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> LOC=L23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> LOC=L24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> LOC=H27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> LOC=H28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> LOC=J27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> LOC=J28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> LOC=K29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> LOC=L29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> LOC=N23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> LOC=N24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> LOC=K27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> LOC=K28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> LOC=R22;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> LOC=M27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> LOC=M28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> LOC=P30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> LOC=P23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> LOC=P24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> LOC=N27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> LOC=N28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> LOC=V27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> LOC=Y30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> LOC=U24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> LOC=U23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> LOC=V26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> LOC=V25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> LOC=Y29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> LOC=AA29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> LOC=Y26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> LOC=AA28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> LOC=AA27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> LOC=W24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> LOC=W23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> LOC=AB28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> LOC=AB27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> LOC=AC29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> LOC=AB25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> LOC=AE29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> LOC=AA24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> LOC=AA23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> LOC=AD28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> LOC=AD27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> LOC=AF30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> LOC=AF29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> LOC=AF25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> LOC=AG30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> LOC=AG29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> LOC=AD26;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> LOC=AD25;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> LOC=AG28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> LOC=AH27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> LOC=AH29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> LOC=AC27;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> LOC=AD29;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> LOC=AB23;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> LOC=AC28;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> LOC=AD30;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> LOC=AB24;
Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_CLK_FB LOC=C16;
Net fpga_0_DDR_CLK_FB IOSTANDARD = SSTL2_II;
Net fpga_0_DDR_CLK_FB_OUT LOC=G23;
Net fpga_0_DDR_CLK_FB_OUT IOSTANDARD = SSTL2_II;