vhdl.txt

VHDL 的一个流水灯程序 开发平台Quartusii 使用的延时方法为分频思想

一个简单的程序，抛砖引玉 有什么问题请留言，有什么好的程序 请留言 呵呵

程序段1：该段程序 是块图 将下面两端程序 生成模块之后连载一起 分频后的十种接到模块 waterlight 模块的时钟端 然后锁定引脚 就可以了


程序段2：流水灯控制程序


-- designed by haoyufu 2008-8-24
-- input clk is 50Mhz
-- fpga：EP2C20F484C8
library ieee ; 
use ieee.std_logic_1164.all; 
entity waterlight is 
port (start : in std_logic; --开始控制键
      stop : in std_logic; --结束控制键
      shift_left : in std_logic; --左移控制键
      Q : out std_logic_vector(7 downto 0); --接8个发光二极管
      clk : in std_logic   --接时钟引脚
      ); 
end waterlight; 
architecture behavior of waterlight is 
signal lights : std_logic_vector(7 downto 0); 
begin
process (clk, start, stop, shift_left) 
begin 
if (start = '0' or stop = '1') then 
lights <= (others => '1'); 
elsif (clk'event and clk = '1') then 
if (shift_left = '1') then 
lights <= lights(6 downto 0) & '0'; 
else 
lights <= '0' & lights(7 downto 1); 
end if; 
end if; 
end process; 
Q <= lights; 
end behavior;

程序段3：分频程序

-- designed by haoyufu 2008-8-24
library ieee ; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
entity fenpin is
port( clk : in std_logic ;
        out_clk : out std_logic );
end;
architecture behav of fenpin is
signal count : integer range 0 to 999999; 
begin 
process(clk)
begin
--count <= 0;   --赋初始值
if clk'event and clk='1' then 
   if count<=499999 THEN                           
          out_clk <='0';      --当count<=499999时divls=0并且count加1
          count<=count+1;                          
        ELSIF count>=499999 AND count<=999999 THEN --当ount>=499999 并且 count<=999998时
               out_clk<='1';           --                             
               count<=count+1; --clk=1并且count加1
        ELSE count<=0; --当count>=499999时清零count1
        END IF;                                                      
     END IF;                                          
   END process ;
end;