📄 ds1302driver_io.asm
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//======================================================
// 文件名称: DS1302Driver_IO.asm
// 功能描述: DS1302底层驱动程序,主要是与时序有关的代码
// 维护记录: 2006-06-14 v1.0
// Mz出品 时序经典
// 注 意: 汇编语言版
//======================================================
// IO port control registers
.DEFINE P_IOA_Data 0x7000
.DEFINE P_IOA_Buffer 0x7001
.DEFINE P_IOA_Dir 0x7002
.DEFINE P_IOA_Attrib 0x7003
.DEFINE P_IOA_Latch 0x7004
.DEFINE P_IOB_Data 0x7005
.DEFINE P_IOB_Buffer 0x7006
.DEFINE P_IOB_Dir 0x7007
.DEFINE P_IOB_Attrib 0x7008
//redefine the I/O port for DS1302
.DEFINE Port_Data P_IOB_Data
.DEFINE Port_Buffer P_IOB_Buffer
.DEFINE Port_Dir P_IOB_Dir
.DEFINE Port_Attrib P_IOB_Attrib
//Define the I/O Port bit connected with DS1302, just as CE\DA\CLK
.DEFINE M_CE 0x8000
.DEFINE M_DA 0x4000
.DEFINE M_CLK 0x2000
.CODE
//======================================================
// 汇编格式: _F_DS1302_Initial_IO
// C格式: void F_DS1302_Initial_IO(void);
// 实现功能: 端口初始化子程序
// 入口参数: 无
// 出口参数: 无
//======================================================
.PUBLIC _F_DS1302_Initial_IO
_F_DS1302_Initial_IO:
r1 = [Port_Dir]
r1 = r1|(M_CE+M_DA+M_CLK)
[Port_Dir] = r1
r1 = [Port_Attrib]
r1 = r1|(M_CE+M_DA+M_CLK)
[Port_Attrib] = r1
r1 = [Port_Buffer]
r1 = r1&(~(M_CE+M_DA+M_CLK))
[Port_Buffer] = r1
r1 = [Port_Data]
r1 = r1|(M_CE+M_DA+M_CLK)
[Port_Attrib] = r1
retf
//======================================================
// 汇编格式: _F_DS1302_WriteByte
// C格式: void F_DS1302_WriteByte(unsigned int Addr,unsigned int Data)
// 实现功能: 写一个字节数据至DS1302的指定地址的空间当中
// 入口参数: Addr 指定的地址
// Data 要写入的数据
// 出口参数: 无
//======================================================
.PUBLIC _F_DS1302_WriteByte
_F_DS1302_WriteByte:
push bp to [sp]
bp = sp+4
r1 = [bp] //get Addr
r1 = r1&0x00ff
r2 = [bp+1] //Get Data
r2 = r2 lsl 4
r1 =r1+r2 lsl 4 //
r4 = 16
r2 = [Port_Buffer]
r2 = r2|M_CE
[Port_Buffer] = r2 //CE to hight ??
?Write_Loop:
test r1,0x0001
jz ?Write_0
r2 = r2|M_DA
jmp ?Write_DD
?Write_0:
r2 = r2&(~M_DA)
?Write_DD:
[Port_Buffer] = r2 //Send Data to the I/O
r3 = r2|M_CLK
[Port_Buffer] = r3 //CLK to Hight
r1 = r1 lsr 1
r4-=1
jz ?Write_Exit
[Port_Buffer] = r2 //CLK to Low
jmp ?Write_Loop
?Write_Exit:
[Port_Buffer] = r2
r2 = r2&(~(M_DA+M_CE))
[Port_Buffer] = r2
pop bp from [sp]
retf
//======================================================
// 汇编格式: _F_DS1302_ReadByte
// C格式: unsigned int F_DS1302_ReadByte(unsigned int Addr)
// 实现功能: 计取DS1302当中指写地址空间的一个字节数据数据
// 入口参数: Addr 指定的地址
// 出口参数: 无
//======================================================
.PUBLIC _F_DS1302_ReadByte
_F_DS1302_ReadByte:
push r5 to [sp]
r4 = 8
r2 = [Port_Buffer]
r2 = r2|M_CE
[Port_Buffer] = r2 //CE to hight ??
?Write1_Loop:
test r1,0x0001
jz ?Write1_0
r2 = r2|M_DA
jmp ?Write1_DD
?Write1_0:
r2 = r2&(~M_DA)
?Write1_DD:
[Port_Buffer] = r2 //Send Data to the I/O
r3 = r2|M_CLK
[Port_Buffer] = r3 //CLK to Hight
r1 = r1 lsr 1
r4-=1
jz ?Read_DD
[Port_Buffer] = r2 //CLK to Low
jmp ?Write1_Loop
?Read_DD:
r1 = [Port_Dir]
r1 = r1&(~M_DA)
[Port_Dir] = r1 //I/O as Floating input
r1 = 0 //Clear r1
r4 = 8
r3 = r2|M_CLK //R3 save the status as CLK is Hight
?Read_Loop:
[Port_Buffer] = r2 //CLK to low
r1 = r1 lsr 1
nop //for clk data delay,if cpuclock is highter,user shoud insert more 'nop'
r5 = [Port_Data] //Read the data of DS1302`s data port
r5 = r5&M_DA
jz ?Read_0
r5 = 0x0080 //lsb first so......
?Read_0:
r1 = r1|r5
[Port_Buffer] = r3 //CLK to hight
r4-=1
jnz ?Read_Loop
r3 = [Port_Dir]
r3 = r3|M_DA
[Port_Dir] = r3 //I/O as Output port
r2 = r2&(~(M_CE+M_CLK))
[Port_Buffer] = r2 //Set the CLK\CE to Low
pop r5 from [sp]
retf
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